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Flags and Error Weight Parities: A Development of Fault-tolerant Quantum Computation with Few Ancillas

Theerapat Tansuwannont

Published Oct 13, 2021• 0 citations
OpenAlex

Abstract

In quantum computation, errors in a quantum circuit arising from its interaction with the environment is one of the biggest obstacles to building large-scale quantum computers. One way to deal with such errors is using fault-tolerant error correction (FTEC), a procedure which suppresses error propagation in a quantum circuit, together with other fault-tolerant gadgets for quantum computation to simulate a quantum circuit. However, for some platforms in which the number of physical qubits is limited, achieving a fault-tolerant simulation with very low logical error rate can be challenging since large overhead is required. \nIn this thesis, flag and weight parity techniques for FTEC which use only small number of ancillas are studied. The flag technique uses a few ancillas in circuits for syndrome measurement to detect high-weight errors arising from a few faults, while the weight parity technique uses weight parities and syndromes of errors to determine whether they are logically equivalent. The concepts of these two techniques can lead to the notion of distinguishable fault set, the central idea for the fault-tolerant protocol development in this thesis. In addition, fault-tolerant protocols for two families of codes are constructed: an FTEC protocol for the [[49,1,9]] concatenated Steane code which can correct up to 3 faults and uses 2 ancillas, and protocols for fault-tolerant quantum computation on capped color codes which require 1, 1, and 2 ancillas for the codes of distance 3, 5, and 7. The concept of distinguishable fault set also leads to a generalization of the definitions of fault-tolerant gadgets which give more flexibility when designing fault-tolerant protocols.

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In quantum computation, errors in a quantum circuit arising from its interaction with the environment is one of the biggest obstacles to building large-scale quantum computers. One way to deal with such errors is using fault-tolerant error correction (FTEC), a procedure which suppresses error propagation in a quantum circuit, together with other fault-tolerant gadgets for quantum computation to simulate a quantum circuit. However, for some platforms in which the number of physical qubits is limited, achieving a fault-tolerant simulation with very low logical error rate can be challenging since large overhead is required. \nIn this thesis, flag and weight parity techniques for FTEC which use only small number of ancillas are studied. The flag technique uses a few ancillas in circuits for syndrome measurement to detect high-weight errors arising from a few faults, while the weight parity technique uses weight parities and syndromes of errors to determine whether they are logically equivalent. The concepts of these two techniques can lead to the notion of distinguishable fault set, the central idea for the fault-tolerant protocol development in this thesis. In addition, fault-tolerant protocols for two families of codes are constructed: an FTEC protocol for the [[49,1,9]] concatenated Steane code which can correct up to 3 faults and uses 2 ancillas, and protocols for fault-tolerant quantum computation on capped color codes which require 1, 1, and 2 ancillas for the codes of distance 3, 5, and 7. The concept of distinguishable fault set also leads to a generalization of the definitions of fault-tolerant gadgets which give more flexibility when designing fault-tolerant protocols.
Fault-tolerant quantum error correction (FTEC) protocol is one of the most important components for a fault-tolerant simulation of a quantum circuit. It helps prevent error accumulation during the process which may cause the computation to fail. In a physical implementation of fault-tolerant circuits, the number of required ancilla qubits for the FTEC protocol can be a major concern because it grows exponentially as the level of concatenation increases whereas the resources are limited. Recently, the idea of using flag qubits to detect high-weight errors caused by fewer faults in syndrome extraction circuits has been proposed. The use of flag qubits allows the construction of fault-tolerant protocols with the fewest number of ancillas known to-date. In this work, some critical properties of CSS codes constructed from classical cyclic codes that enable the construction of a flag fault-tolerant error correction scheme are proved, and a fault-tolerant protocol along with a family of circuits for flag fault-tolerant error correction are given. The flag-FTEC protocol proposed in this work requires only four ancilla qubits and applicable to CSS codes of distance 3 constructed from classical cyclic codes.
Fault-tolerant error-correction (FTEC) circuit is the foundation for achieving reliable quantum computation and remote communication. However, designing a fault-tolerant error correction scheme with a solid error-correction ability and low overhead remains a significant challenge. In this paper, a low-overhead fault-tolerant error correction scheme is proposed for quantum communication systems. Firstly, syndrome ancillas are prepared into Bell states to detect errors caused by channel noise. We propose a detection approach that reduces the propagation path of quantum gate fault and reduces the circuit depth by splitting the stabilizer generator into X-type and Z-type. Additionally, a syndrome extraction circuit is equipped with two flag qubits to detect quantum gate faults, which may also introduce errors into the code block during the error detection process. Finally, analytical results are provided to demonstrate the fault-tolerant performance of the proposed FTEC scheme with the lower overhead of the ancillary qubits and circuit depth.
Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary. In this work, we combine flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. We further show an example of performing the Steane code error correction on two current superconducting processors and numerically analyze their performance with circuit level noise. The simulation results show that the QEC circuits that measure more stabilizers in parallel have lower logical error rates. We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, we foresee potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques.
In this paper we introduce a general fault-tolerant quantum error correction protocol using flag circuits for measuring stabilizers of arbitrary distance codes. In addition to extending flag error correction beyond distance-three codes for the first time, our protocol also applies to a broader class of distance-three codes than was previously known. Flag circuits use extra ancilla qubits to signal when errors resulting from v faults in the circuit have weight greater than v . The flag error correction protocol is applicable to stabilizer codes of arbitrary distance which satisfy a set of conditions and uses fewer qubits than other schemes such as Shor, Steane and Knill error correction. We give examples of infinite code families which satisfy these conditions and analyze the behaviour of distance-three and -five examples numerically. Requiring fewer resources than Shor error correction, flag error correction could potentially be used in low-overhead fault-tolerant error correction protocols using low density parity check quantum codes of large code length.
Color codes are promising quantum error-correction (QEC) codes because they have an advantage over surface codes in that all Clifford gates can be implemented transversally. However, the thresholds of color codes under circuit-level noise are relatively low, mainly because measurements of their high-weight stabilizer generators cause an increase in the circuit depth and, thus, substantial errors are introduced. This makes color codes not the best candidate for fault-tolerant quantum computing. Here, we propose a method to suppress the impact of such errors by optimizing weights of decoders using conditional error probabilities conditioned on the measurement outcomes of flag qubits. In numerical simulations, we improve the threshold of the (4.8.8) color code under circuit-level noise from 0.14% to around 0.27%, which is calculated by using an integer programming decoder. Furthermore, in the (6.6.6) color code, we achieve a circuit-level threshold of around 0.36%, which is almost the same value as the highest value in the previous studies employing the same noise model. In both cases, the effective code distance is also improved compared to a conventional method that uses a single ancilla qubit for each stabilizer measurement. Thereby, the achieved logical error rates at low physical error rates are almost one order of magnitude lower than those of the conventional method with the same code distance. Even when compared to the single-ancilla method with a higher code distance, considering the increased number of qubits used in our method, we achieve lower logical error rates in most cases. This method can also be applied to other weight-based decoders, making the color codes more promising as candidates for the experimental implementation of QEC. Furthermore, one can utilize this approach to improve a threshold of wider classes of QEC codes, such as high-rate quantum low-density parity-check codes. Published by the American Physical Society 2024
Building reliable quantum computers requires protecting fragile quantum states from inevitable environmental noise and operational errors. While quantum error correction codes like the Steane [ ⁣[7,1,3] ⁣][\![7,1,3]\!][[7,1,3]] code provide elegant theoretical solutions, their practical success hinges critically on how we measure errors - a process called syndrome extraction. The challenge lies in the ancilla qubits used for measurement: when they fail, errors can cascade across the entire quantum system, destroying the very information we're trying to protect. We address this fundamental problem by implementing and comparing three sophisticated syndrome measurement strategies: Shor's cat-state approach, which distributes measurements across multiple entangled ancillas achieving 85-92% preparation success; Steane's encoded-ancilla method using complete error-corrected logical qubits reaching 97.8% syndrome fidelity; and a flexible unified framework that adapts strategies based on hardware capabilities. Through extensive simulations using IBM's Qiskit platform spanning randomized benchmarking and T-heavy circuits, we demonstrate that intelligent ancilla management improves error suppression by up to 2.4×\times× compared to standard approaches. Our implementations achieve logical error rates as low as 5.1×10−55.1 \times 10^{-5}5.1×10−5 under realistic noise conditions with physical error rates of 10−310^{-3}10−3, while maintaining near-unity logical fidelity (0.99997) even for deep circuits. The threshold analysis reveals robust performance across distance-3 to distance-13 codes with characteristic threshold curves showing exponential error suppression below the critical physical error rate. These results provide immediately deployable tools for near-term quantum devices and establish practical design principles for scaling toward fault-tolerant quantum computers.