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Bulletin of the American Physical Society

Quantum error correction with trapped ions

Philipp Schindler

Published Mar 16, 2016• 0 citations
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Bulletin of the American Physical Society•Apr 18, 2021•0 citations
In order to carry out different quantum algorithms on the same quantum circuit, we have to start the next algorithm from the qubit arrangement at the end of the previous one. The arrangement of trapped ions after some algorithm execution is generally not optimal for the following algorithm in an ion-trap quantum computer. We simulated the sequences in the Grover's quantum circuits for searching an unsorted database in order to obtain sequence error rates under a random initial arrangement of qubits. When the sequence error rate for the circuit with QEC is less than that for the circuit without QEC, it is worth introducing the QEC circuit. From the condition, we obtained the quantum error correction criteria that depends on two parameters: concentrations flip of qubits and error rates. If we can know the flip error rate in an ion-trap quantum computer and determine the concentration, the criteria help us to realize a quantum circuit execution with less error rates in an ion-trap quantum computer.
We construct a detailed microscopic noise model for multi-qubit (MQ) gate operations in the context of trapped ion architecture with all-to-all connectivity. We find that phonon heating and motional dephasing are well captured by effective single- and two-qubit error channels that can, in principle, act between arbitrary pairs of qubits. Nevertheless, the median magnitude of two-qubit errors between uncoupled qubits is substantially smaller than that of errors between gate-coupled qubits. Errors associated with photon scattering are shown to solely propagate to qubits participating in gate operations. Lastly, we combine all noise sources, assigned with experimentally relevant parameters, and explore the scalability of a quantum error correction (QEC) scheme based on the rotated surface code, as a function of error rates and code size. Our analysis bridges device-level physics and QEC performance for MQ gates in trapped-ion architectures.