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Radio Engineering

Research on LDPC Codes Decoding Algorithm for High Data Rate Transmission

Lei Guang-xiong

Published Jan 1, 2011• 0 citations
OpenAlex

Abstract

This paper analyzes the complexity and capability of different decoding algorithms for LDPC code based on in-depth study of the theory of decoding algorithms.An improved min-sum decoding algorithm is proposed.The simulation results demonstrate that the proposed algorithm reduces the computation complexity,decreases the average iterations and improves the convergence property.Therefore,this modified decoding algorithm is highly valuable for hardware implementation.

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Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1

WSEAS TRANSACTIONS on COMMUNICATIONS archive•Jul 1, 2009•1 citation
This paper analyzes the complexity and capability of different decoding algorithms for LDPC code based on in-depth study of the theory of decoding algorithms.An improved min-sum decoding algorithm is proposed.The simulation results demonstrate that the proposed algorithm reduces the computation complexity,decreases the average iterations and improves the convergence property.Therefore,this modified decoding algorithm is highly valuable for hardware implementation.
The simple algorithms based on belief propagation algorithm of LDPC codes are studied.A modified algorithm which integrates Row Message Passing schedule with Offset Min-Sum algorithm for decoding LDPC codes is proposed.The proposed algorithm facilitates hardware implementation because it improves the convergence property while its computation complexity is the same as Offset Min-Sum algorithm,and it reduces the storage for the optimized memory method.The simulation results demonstrate that the proposed algorithm reduces the average iterations and quantization implementation memory.
Low-Density Parity check (LDPC) codes offer high-performance error correction near the Shannon limit which employs large code lengths and some iterations in the decoding process. The conventional decoding algorithm of LDPC is the Log Likelihood Ratio based Belief Propagation (LLR BP) which is also known as the `Sum-Product algorithm' which gives the best decoding performance and requires the most computational complexity and implementations with increased hardware complexity. Another simpler variant of this algorithm is used which is known as `min-sum algorithm' which reduces computational complexity as well as hardware complexity but with reduced accuracy. This paper analyzes the reason min-sum algorithm is more prone to errors when compared to the sum-product algorithm, and puts forward two improved algorithms which improve the performance of the min-sum algorithm with comparable algorithmic complexity.
Among the decoding algorithms for low-density parity-check(LDPC) code,sum-product algorithm(SPA) has the optimal performance but high complexity,while min-sum algorithm has simple implementation complexity but worse performance.Considering this performance-complexity contradiction,some modified min-sum algorithms are proposed.In this paper,researches are done based on one of the modified min-sum algorithms that is close to SPA in performance but the way modifying fraction works is simplified.Simplified algorithm remains similar in performance to sum-product algorithm but has a remarkably reduced implementation complexity.
Based on the demand for hardware implementation,the paper presents the decoding algorithm of LDPC code and proposes a new modification factor for Normalized Min-Sum algorithm to ease the hardware implementation.This paper describes the simulations on the performances of quantization range and quantization scheme.Simulation results show that the performances of 5,6 or 7 quantization bits are all quite close to ideal performance.This algorithm would reduce greatly the computation complexity and the difficulty in hardware implementation.
Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.
Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1