The Single Flux Quantum(SFQ) pulse transmission between cells plays an important role in superconducting SFQ digital circuit layout design.In this paper,we review the SFQ interconnection schemes with transmission line between SFQ digital cells and provided a close form for the transmission line match circuit calculation.The corresponding simulations based on the formula show the reliable pulse transmission between SFQ circuits can be achieved satisfactorily.
The Single Flux Quantum(SFQ) pulse transmission between cells plays an important role in superconducting SFQ digital circuit layout design.In this paper,we review the SFQ interconnection schemes with transmission line between SFQ digital cells and provided a close form for the transmission line match circuit calculation.The corresponding simulations based on the formula show the reliable pulse transmission between SFQ circuits can be achieved satisfactorily.
We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.
Single-flux-quantum (SFQ) digital circuits are mostly based on cells that rely on reliable foundry processes that make use of a superconducting ground plane as a reference for the active elements and the microstrip line interconnects. The quantum of magnetic flux h/2e, associated with the binary information, corresponds to a magnetic field energy density that needs to be localized in space to limit interactions between adjacent cells. In other words, mutual inductances can harm the proper behaviour of circuits unless they are taken carefully into account during the design phase. We studied extensively the Josephson transmission line cell with different geometrical configurations of the ground plane and bias pads. We found with the use of InductEx that the return current sometimes follows paths that are far from what intuition tells, which can lead to nonoptimized designs. In this paper, we emphasize the limitations due to the presence of external or internal magnetic fields. Then, we compare obtained performances with the ones with optimized geometries for which the presence of the magnetic field is taken into account from the design phase.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 4 x 4 switch having block-to-block passive interconnections and a 2 x 2 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFO circuits having passive interconnections.
The authors analyzed, designed, and tested drivers and receivers which make it possible to connect distant circuits of the rapid single-flux-quantum (RSFQ) logic/memory family by passive superconducting microstrip lines. Using these circuits implemented with a niobium trilayer fabrication technology, reliable transmission and reception of the SFQ pulses over distances up to 1 cm, with margins of bias currents as wide as +or-30%, have been demonstrated. The pulses can be passed along wide lines (20 mu m for 3.5 mu Nb-Al/sub 2/O/sub 3/-Nb Josephson junction technology) over such distances and can be picked up by the RSFQ receiver.>
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.