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Journal of Naval University of Engineering

Low complexity algorithm for decoding LDPC codes

Wenjuan Zhang

Published Jan 1, 2010• 0 citations
OpenAlex

Abstract

A low complexity algorithm(combined sum-product algorithm,CSPA)for decoding lowdensity parity-check codes is proposed,which works based on the sum-product algorithm(SPA)at first,and then switches to the selective node update(SNU)algorithm after most of the message has been converged.The computer simulations show that at a moderate code length,the proposed algorithm can overcome the deficiencies in SNU algorithm for its slow convergence rate and high error platform and effectively reduce the complexity in computation with little loss in the BER performance when compared with SPA.

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A low complexity algorithm(combined sum-product algorithm,CSPA)for decoding lowdensity parity-check codes is proposed,which works based on the sum-product algorithm(SPA)at first,and then switches to the selective node update(SNU)algorithm after most of the message has been converged.The computer simulations show that at a moderate code length,the proposed algorithm can overcome the deficiencies in SNU algorithm for its slow convergence rate and high error platform and effectively reduce the complexity in computation with little loss in the BER performance when compared with SPA.
Efficient implementations of the sum-product algorithm (SPA) are presented for decoding low-density parity-check (LDPC) codes using log-likelihood ratios (LLR) as messages between symbol and parity-check nodes. Various reduced-complexity derivatives of the LLR-SPA are proposed. Both serial and parallel implementations are investigated, leading to trellis and tree topologies, respectively. Furthermore, by exploiting the inherent robustness of LLRs, it is shown, via simulations, that coarse quantization tables are sufficient to implement complex core operations with negligible or no loss in performance. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate design point in high-speed applications from a performance, latency and computational complexity perspective.
A complexity-and delay-efficient simplification of the sum-product algorithm (SPA) for decoding lowdensity parity-check (LDPC) codes is presented. The key feature of the new algorithm consists of a modification of the complexity-intensive and delay-causing update equations at the check nodes of the factor graph of the LDPC code. The modified update equations at a check node are based on ordering the reliability values of the incoming messages and on using a balanced tree topology to achieve optimum parallel processing. Furthermore, the complexity of the new algorithm can be adjusted: the least complex version of the algorithm corresponds to the so-called min-sum approximation, and the most complex version gives the full SPA.
This letter proposes a new algorithm for the check node update in the decoding of low-density parity-check (LDPC) codes. The proposed algorithm is based on a new approximation formula of standard sum-product algorithm (SPA) which can reduce the approximation error of min-sum algorithm (MSA) and has almost the same performance as sum-product algorithm (SPA) under both floating precision operation and fixed-point operation. Besides, the new approximation formula can be implemented in simple structures competitive with MSA.
In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function Psi(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT. Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of readonly-memory (ROM) for LUT
Among the decoding algorithms for low-density parity-check(LDPC) code,sum-product algorithm(SPA) has the optimal performance but high complexity,while min-sum algorithm has simple implementation complexity but worse performance.Considering this performance-complexity contradiction,some modified min-sum algorithms are proposed.In this paper,researches are done based on one of the modified min-sum algorithms that is close to SPA in performance but the way modifying fraction works is simplified.Simplified algorithm remains similar in performance to sum-product algorithm but has a remarkably reduced implementation complexity.