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Radio Engineering of China

A Higher Throughput LDPC Decoding Algorithm

Wenzhe Jiang

Published Jan 1, 2008• 0 citations
OpenAlex

Abstract

In order to design an efficient decoder of LDPC,combining the regularity of check matrix H of Quasi-cyclic LDPC,the characteristic of NMSA(normal min-sum algorithm)that don't have to evaluate the quality of the channel and the characteristic of partially parallel decoding that the implementing complexity is low,we described a new decoding algorithm,overlapped partially parallel decoding algorithm,which can not only lower the complexity of implementation and the overhead of memory but also improve the throughput of decoder in comparison with decoding algorithm of partially parallel.

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In order to design an efficient decoder of LDPC,combining the regularity of check matrix H of Quasi-cyclic LDPC,the characteristic of NMSA(normal min-sum algorithm)that don't have to evaluate the quality of the channel and the characteristic of partially parallel decoding that the implementing complexity is low,we described a new decoding algorithm,overlapped partially parallel decoding algorithm,which can not only lower the complexity of implementation and the overhead of memory but also improve the throughput of decoder in comparison with decoding algorithm of partially parallel.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
In this work, a high performance LDPC decoder architecture is presented. It is a partially-parallel architecture for low-complexity consideration. In order to eliminate the idling time and hardware complexity in conventional partially-parallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the parity-check matrix is optimally partitioned into four unequal sub-matrices that lead to high efficiency in hardware sharing. As a result, it can handle two different codewords simultaneously with 100% hardware utilization. Furthermore, for minimizing the performance loss due to round-off errors in fixed-point implementations, the well-known modified min-sum decoding algorithm is enhanced by our recently proposed high-performance CMVP decoding algorithm. Overall, the proposed decoder has high throughput, low complexity, and good BER performances. In the circuit implementation example of the (576, 288) parity check matrix for IEEE 802.16e standard, the decoder achieves a data rate of 5.5Gbps assuming 10 decoding iterations and 7 quantization bits, with a small area of 653K gates, based on UMC 90nm process technology.
In this paper, a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check codes using (modified) min-sum decoding algorithm is proposed. In general, more than thirty percent of memory can be saved over conventional partially parallel decoder architectures. To reduce the computation delay of check-node processing unit, an efficient architecture based on variants of rank order filter is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems
This paper presents an efficient general-purpose QC-LDPC decoder architecture by combining hardware with software.The proposed architecture can be applied to regular and irregular QC-LDPC codes of various rates,lengths and parity-check matrix structures,and supports min-sum approximation decoding algorithms and realizes different message passing scheduling strategies.Some complicated message update is implemented by a hardware accelerator,thus the decoding throughput is improved.According to the quasi-cyclic structure of the parity-check matrix,the messages are stored and processed by blocks in decoding.Parallel message processing can also be realized with a small increase in implementation complexity.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. For the first time, this paper proposes a partial-parallel decoder architecture based on the Min-max algorithm for quasi-cyclic NB-LDPC codes. A novel boundary tracking based scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In addition, layered decoding is applied, and the hardware units are optimized to reduce the latency and area. This paper also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity analysis, the proposed decoder with 5 iterations for a (837,726) code over GF(25) can easily achieve 60 Mbps throughput on ASIC devices. It is 40% more efficient than prior designs.
Nonbinary low-density parity-check (NB-LDPC) codes constructed over GF(q) (q >; 2) can achieve higher coding gain than binary LDPC codes when the code length is moderate. A complete partial-parallel decoder architecture based on the Min-max algorithm is proposed for quasi-cyclic NB-LDPC codes in this paper. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm5) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out.