A kind of regular LDPC codes is introduced.Its error correcting capability is better than Turbo codes' and approaches to Shannon limit(1.2 dB).The construction of the sparse parity matrix is important,which affects the LDPC codes' error correcting capability.In this paper,the diagonal method is adopted to construct sparse check matrix of(n,3,6) in approximate lower triangle,which meets the numbers of and distribution randomicity of nonzero elements.The belief propagation algorithm is used in decoding simulation,and the vectorization method is proposed to reduce the iteration decoding time.
A kind of regular LDPC codes is introduced.Its error correcting capability is better than Turbo codes' and approaches to Shannon limit(1.2 dB).The construction of the sparse parity matrix is important,which affects the LDPC codes' error correcting capability.In this paper,the diagonal method is adopted to construct sparse check matrix of(n,3,6) in approximate lower triangle,which meets the numbers of and distribution randomicity of nonzero elements.The belief propagation algorithm is used in decoding simulation,and the vectorization method is proposed to reduce the iteration decoding time.
A kind of regular LDPC codes is introduced. Its error correct ability is better than Turbo codes' and near to Shannon limit (1.2 dB). The construct of the sparse parity matrix is important. This effects the LDPC codes' error correct ability. In this paper, diagonal method is adopted to construct sparse check matrix of (n,3,6) in approximate lower triangular form by it. This meets the numbers of nonzero elements and randomness. The Belief Propagation algorithm is used in decoding simulation, to this, vector method is proposed which reduces operation time.
Wireless digital communication enables instantaneous connections and conversations between people all over the world. In a digital communication system, the channel code is used to detect and fix errors. The most widely used error-correcting codes are LDPC channel codes, which are represented by a sparse parity-check matrix and have performance close to the Shannon limit. The sophistication and versatility of decoders determines the error-correcting codes' efficacy. LDPC codes are used in a wide variety of broadcasting, satellite communication, LAN, and PAN applications because of their capacity-approaching properties. Sparsity allows for the use of LDPC codes; however, simplified decoding algorithms play a crucial role in achieving high-speed, error-free communication. In this work, we focus on locating a decoding algorithm with the lowest possible complexity and the fewest possible iterations. The belief propagation algorithm and layered decoding or turbo decoding algorithms are with the code rates ½, ¾,5/8, and 13/16, which are compatible with the WLAN (IEEE Std 802.11™-2016 (Revision of IEEE Std 802.11-2012, 2012) standard. In terms of bit error rate, layered decoding or turbo decoding of the message forwarding method performs better. It is also seen that performance improves with an increase in the number of iterations.
Low density parity check codes are a popular class of linear block codes for forward error correction in communication channels. Recent years have seen a lot of work towards the hardware-oriented constructions for LDPC codes which have comparable error-correcting performance to random construction codes. This paper proposes a novel method called Iterative-filled (IF) to construct LDPC codes and a new kind of LDPC codes named IF-LDPC codes. Based on the properties of the method proved in this paper, we present a design of regular and quasi-regular IF-LDPC encoders which have linear encoding complexity, simple construction, low memory requirement and are suitable for partly parallel decoding. These advantages make them easy to hardware implementation. The IF-LDPC codes exhibit good performance in computer simulations and some even better than MacKay codes.
Low density parity checking codes (LDPC) are one of the most important issues in coding theory at present. LDPC-code are a type of linear-block LDPC-codes. Channel coding might be considered as the finest conversant and most potent components of cellular communications systems, that was employed for transmitting errors corrections imposed by noise, fading and interfering. LDPC-codes are advanced coding gain, i.e., new area in coding. the performances of LDPC-code are similar to the Shannon-limiting, this led to the usage of decoding in several applications in digital communications systems, like DVB-S2 and WLAN802.1..This paper aims to know what is LDPC,what its application and introduce encoding algorithms that gives rise to a linear encoding time and also show that the regular and irregular LDPC performance and also introduce different methods for decoding LDPC. I discuss in detail LDPC decoding algorithm: bit flipping algorithm, as a type from hard decision .belief propagation algorithm, sum product algorithm and minimum sum algorithm as examples from soft decision .I expect that at least some students or researchers involved in researching LDPC codes would find this paper helpful.
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.
There is an important breakthrough in the field of forward error correction techniques, low-density parity-check (LDPC) codes. These codes have potential to approach the Shannon limit with reliable performance on a given channel, known as the channel capacity. Recently, researchers pay much more attention towards LDPC codes because its performance is better than Turbo codes. However, the LDPC code is the best when it is an irregular code and uses with a very large block-length. Although, the short block-length LDPC codes perform not so well, they are easy to implement in various practical applications. Therefore, there is still a demand of new development on the encoding side of LDPC codes for various ranges of code rate and code length so as to capable of using in many applications.This thesis proposes the development of quasi-cyclic (QC) LDPC codes for column weight 3. In the first part of this thesis, we propose a new construction algorithm of QC-LDPC codes for medium to large block-length by combining QC-LDPC codes of small block-length as their component codes, via Chinese remainder theorem (CRT). Such component codes were constructed by permuting each column block sequentially to attain the desire local girth. After combining all component codes to generate an expanded parity-check matrix, the resulting girth is greater than or at least equal to the maximum girth of the component codes. Simulation results show that our proposed construction method of the parity-check matrix significantly outperforms the other well-known existing methods in terms of low error-floor, simple structure, high performance, and can reduce encoding complexity.In addition, this thesis also proposes two new construction methods for QC-LDPC codes, namely a base matrix method and a subtraction based method. A base matrix based method is a simple, less computational complexity method for constructing the exponent matrix (3, K) of girth 8, 10 and 12 of QC-LDPC codes. Another method is a subtraction method, which has a similar exponent matrix as a base matrix method and has a girth at least 8. Results indicate that the LDPC codes constructed from these two methods have flexibility for arbitrary block-column length K and have a similar BER performance if compared to existing methods.