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Circuits and Systems

Design and Implementation of Efficient Reversible Arithmetic and Logic Unit

Saravanan Subramanian, Ila Vennila, Sudha Mohanram

Published Jan 1, 2016• 4 citations
Publisher

Abstract

In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.

DOI
10.4236/cs.2016.76054

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In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.
In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.
Reversible logic has emerged as a promising paradigm in various domains, such as low power VLSI design, quantum cellular automata, and nanotechnology-based systems. The arithmetic logic unit (ALU) is one of the main components of any central processing unit. In this paper we propose two new reversible ALUs using elementary quantum gates, with more functions compared to the existing designs. The results show that the proposed designs are better than the existing counterparts in terms of cost-metrics and the number of functions generated. The proposed reversible ALUs can be used in the implementation of quantum computers. All the designs are with nanometric scales.
In the current scenario, power consumption, speed, size and heat dissipation are the huge challenge in the semiconductor industries. When the size of the single computing element is reduced then the speed can be improved and also if the power dissipation is reduced then the heat dissipation will be less. The possible solution for these two problems is the Reversible Logic and Quantum Cellular Automata (QCA). The Reversible Logic is considered to be the promising technology to the future Quantum computer technologies. The Reversible Logic gates prune the power dissipation to a larger extent. In this paper Novel Reversible Gates are proposed with Reversibility and Universality. The Arithmetic and Logic Unit (ALU) is designed with the proposed Reversible Gates in Reversible Logic. The designed Arithmetic and Logic unit is evaluated in QCA with the required specifications. The Arithmetic and Logic Unit is designed by setting the control inputs for each unit. The parameters taken into account are Quantum Cost (QC), Garbage Outputs (GO), Constant Inputs (CI), Area, Number of Cells and Simulation Time. The proposed ALU adopting Novel gates finds utilization in low power applications. Also it can be used as the module in the Quantum computers due to its reduced Quantum Cost and Garbage outputs. The Proposed design extends its applications over Quantum Computing, Optical Computing, Nanotechnology and DNA mapping.
Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss.Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic.This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers.The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach.The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures.Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications.The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.
This paper presents novel one bit arithmetic and logical unit (ALU) design using basic reversible gates. Two designs for both the arithmetic and the logical unit are proposed and one design for the control unit is also put forward. These designs are integrated together to give four complete ALU designs. Each of the proposed design has been implemented in Verilog HDL using Xilinx ISE Suite 14.1 software to verify its functionality. The proposed designs are compared based on quantum cost, garbage outputs and ancilla inputs with their existing counterparts. The simplicity and the reduced quantum cost of the proposed ALU designs, when compared to the existing ones, makes them ideal candidates to be used as modules in quantum computers. The proposed ALUs extend their applications to cryptography, machine learning and nanotechnology.
A function is reversible if each input vector produces a unique output vector. Reversible logic is of growing importance to many future computer technologies. In this paper, the design of a reversible Arithmetic Logic Unit (ALU) is presented making use of multiplexer unit as well as control signals. ALU is one of the most important components of CPU that can be part of a programmable reversible computing device such as a quantum computer. In multiplexer based ALU the operations are performed depending on the selection line. The control unit based ALU is developed with 9n elementary reversible gates for four basic arithmetic logical operations on two n-bit operands. The series of operations are performed on the same line depending on control signals, instead of selecting the desired result by a multiplexer. The later design is found to be advantageous over the former in terms of number of garbage outputs and constant inputs produced.