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Journal of Lightwave Technology

Iteration-Aware LDPC Code Design for Low-Power Optical Communications

Toshiaki Koike–Akino, David S. Millar, Keisuke Kojima, Kieran Parsons, Yoshikuni Miyata, Kenya Sugihara, Wataru Matsumoto

Published Sep 11, 2015• 38 citations
Publisher

Abstract

Recent low-density parity-check (LDPC) codes have shown capacity-approaching performance for various communications systems. However, their promising performance cannot always be obtained due to practical constraints, such as finite codeword length, finite iteration, finite memory, and finite precision. In this paper, we focus on a practical design method of high-performance LDPC codes under a constraint of finite-iteration decoding for low-power optical communications. We introduce an iteration-aware LDPC code design approach, which is based on decoding trajectory in extrinsic information transfer chart analysis. It is demonstrated that an LDPC code designed by the conventional curve-fitting method exhibits nearly 2 dB of penalty, when the maximum number of iterations is limited. The results suggest that the LDPC code should be adaptively changed, e.g., when the number of decoding iterations is decreased to save power consumption. We also extend our design method to a multi-objective optimization concept by taking average degrees into account, so that the threshold and the computational complexity are minimized at the same time. The proposed Pareto-optimal codes can achieve additional 2-dB gain or 50% complexity reduction at maximum, in low-power decoding scenarios.

DOI
10.1109/jlt.2015.2477881

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Recent low-density parity-check (LDPC) codes have shown capacity-approaching performance for various communications systems. However, their promising performance cannot always be obtained due to practical constraints, such as finite codeword length, finite iteration, finite memory, and finite precision. In this paper, we focus on a practical design method of high-performance LDPC codes under a constraint of finite-iteration decoding for low-power optical communications. We introduce an iteration-aware LDPC code design approach, which is based on decoding trajectory in extrinsic information transfer chart analysis. It is demonstrated that an LDPC code designed by the conventional curve-fitting method exhibits nearly 2 dB of penalty, when the maximum number of iterations is limited. The results suggest that the LDPC code should be adaptively changed, e.g., when the number of decoding iterations is decreased to save power consumption. We also extend our design method to a multi-objective optimization concept by taking average degrees into account, so that the threshold and the computational complexity are minimized at the same time. The proposed Pareto-optimal codes can achieve additional 2-dB gain or 50% complexity reduction at maximum, in low-power decoding scenarios.
The optimal performance-complexity tradeoff for error-correcting codes at rates strictly below the Shannon limit is a central question in coding theory. This paper proposes a numerical approach for the minimization of decoding complexity for long-block-length irregular low-density parity-check (LDPC) codes. The proposed design methodology is applicable to any binary-input memoryless symmetric channel and any iterative message-passing decoding algorithm with a parallel-update schedule. A key feature of the proposed optimization method is a new complexity measure that incorporates both the number of operations required to carry out a single decoding iteration and the number of iterations required for convergence. This paper shows that the proposed complexity measure can be accurately estimated from a density-evolution and extrinsic-information transfer chart analysis of the code. A sufficient condition is presented for convexity of the complexity measure in the variable edge-degree distribution; when it is not satisfied, numerical experiments nevertheless suggest that the local minimum is unique. The results presented herein show that when the decoding complexity is constrained, the complexity-optimized codes significantly outperform threshold-optimized codes at long block lengths, within the ensemble of irregular codes.
The design of low-density parity-check (LDPC) code ensembles optimized for a finite number of decoder iterations is investigated. Our approach employs EXIT chart analysis and differential evolution to design such ensembles for the binary erasure channel and additive white Gaussian noise channel. The error rates of codes optimized for various numbers of decoder iterations are compared and it is seen that in the cases considered, the best performance for a given number of decoder iterations is achieved by codes which are optimized for this particular number. The design of generalized LDPC (GLDPC) codes is also considered, showing that these structures can offer better performance than LDPC codes for low-iteration-number designs. Finally, it is illustrated that LDPC codes which are optimized for a small number of iterations exhibit significant deviations in terms of degree distribution and weight enumerators with respect to LDPC codes returned by more conventional design tools.
The design of low-density parity-check (LDPC) code ensembles optimized for a finite number of decoder iterations is investigated. Our approach employs EXIT chart analysis and differential evolution to design such ensembles for the binary erasure channel and additive white Gaussian noise channel. The error rates of codes optimized for various numbers of decoder iterations are compared and it is seen that in the cases considered, the best performance for a given number of decoder iterations is achieved by codes which are optimized for this particular number. The design of generalized LDPC (GLDPC) codes is also considered, showing that these structures can offer better performance than LDPC codes for low-iteration-number designs. Finally, it is illustrated that LDPC codes which are optimized for a small number of iterations exhibit significant deviations in terms of degree distribution and weight enumerators with respect to LDPC codes returned by more conventional design tools.
The stopping criterion based on parity-check constraints is an inherent advantage of low-density parity-check (LDPC) codes. However, the parity-check computation with signs of the posterior information costs additional hardware or decoding delays, which may be a particular problem for the full-parallel LDPC decoding in optical transmission. Furthermore, the performance degradation caused by using simplified stopping criterions should also be considered, where the maximum number of the iterations is usually limited by the very high decoding speed in optical transmission. In this paper, we propose an efficient early stopping criterion with the consideration of the complexity/performance tradeoffs. The new method is based an intelligent combination of check equations and temporary hard decisions, and can be pipelined with check-node updating, thus leading to lower complexity and power consumption, which are desirable for both optical and wireless communications. Simulation results show that the hybrid criterion not only achieves the same performance as the conventional stopping criterions, but also provides a noticeable gain for the other simplified stopping criterions.
In this letter, we present a design method to find good protograph-based low-density parity-check codes with the numbers of nonzero elements in the parity-check matrix and decoding iterations both strictly limited. We utilize the protograph-based extrinsic information transfer (PEXIT) analysis to evaluate the error performance and employ the differential evolution algorithm to devise a well-performed coding scheme. In particular, the number of iterations in the PEXIT analysis is set to a small value due to the limited iterations in the decoding process. Both numerical analyses and simulations verify that the resulting codes exhibit better performance than conventional code designs under the limitation of decoding complexity.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area. This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.