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EPJ Techniques and Instrumentation

Fabrication of ion-trap electrodes by self-terminated electrochemical etching

Zhao Wang, Le Luo, Karthik Thadasina, Kim Qian, Jin‐Ming Cui, Yun‐Feng Huang

Published Mar 17, 2016• 6 citations
Publisher

Abstract

Self-terminated electrochemical etching is applied to fabricate needle electrodes for ion traps. We study the surface morphology of the electrodes with scanning electron microscopy and atomic force microscopy, and find that the surface curvature and roughness can be reduced by optimizing the etching parameters. Our method provides a convenient and low-cost solution to improve the surface quality of electrodes for ion traps.

DOI
10.1140/epjti/s40485-016-0030-5

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Self-terminated electrochemical etching is applied to fabricate needle electrodes for ion traps. We study the surface morphology of the electrodes with scanning electron microscopy and atomic force microscopy, and find that the surface curvature and roughness can be reduced by optimizing the etching parameters. Our method provides a convenient and low-cost solution to improve the surface quality of electrodes for ion traps.
Despite the progress in building sophisticated microfabricated ion traps, Paul traps employing needle electrodes retain their significance due to the simplicity of fabrication while producing high-quality systems suitable for quantum information processing, atomic clocks, etc. For low noise operations such as minimizing "excess micromotion," needles should be geometrically straight and aligned precisely with respect to each other. Self-terminated electrochemical etching, previously employed for fabricating ion-trap needle electrodes, employs a sensitive and time-consuming technique, resulting in a low success rate of usable electrodes. Here, we demonstrate an etching technique for the quick fabrication of straight and symmetric needles with a high success rate and a simple apparatus with reduced sensitivity to alignment imperfections. The novelty of our technique comes from using a two-step approach employing turbulent etching for fast shaping and slow etching/polishing for subsequent surface finish and tip cleaning. Using this technique, needle electrodes for an ion trap can be fabricated within a day, significantly reducing the setup time for a new apparatus. The needles fabricated via this technique have been used in our ion trap to achieve trapping lifetimes of several months.
The surface-electrode ion trap is one of the most promising devices to realize large-scale and integrated quantum information processing. However, a series of problems are faced in the micro-nano fabrication of surface-electrode ion traps. A prominent one is the difficulty to control the thick film surface roughness. A rough electrode surface could produce excessive radio frequency (RF) loss and deteriorate trapping ability of the surface-electrode ion trap. In this paper, a thick film micro-nano fabrication technology to control the surface roughness is presented, which can reduce the roughness of thick film surface-electrode down to 6.2 nm, while being controllable between 6.2 nm and 45 nm. Therefore, it can also provide a basis for studying the influence of electrode surface roughness on trap performance. The micro-nano fabrication technology is not only suitable for surface-electrode ion traps with various configurations, but also be further applied to researches of MEMS, solar cells and surface science.
This paper presents a new microfabrication method for surface ion traps and experimental results with trapped ions. Fabricating ion trap chips is a very formidable task because the top electrodes are vertically spaced more than 10 µm from the bottom electrodes with an indented dielectric layer in the middle. Previous ion traps were fabricated using TEOS timed etch or tungsten sacrificial etch techniques. This paper presents a new microfabrication method, using copper as a sacrificial material for an aluminum-oxide-aluminum ion trap structure. Using the developed method the overhang dimensions of the top aluminum electrodes can be accurately controlled. Fabricated ion trap chips are installed in a 1 × 10−11Torr vacuum environment for ion trapping experiments. Successful results in trapping strings of171Yb+and174Yb+ions as well as manipulating171Yb+ions for qubit operation are demonstrated.
Trapped ions offer long internal state (spin) coherence times and strong interparticle interactions mediated by the Coulomb force. This makes them interesting candidates for quantum simulation of coupled lattices. To this end, it is desirable to be able to trap ions in arbitrary conformations with precisely controlled local potentials. We provide a general method for optimizing periodic planar radio-frequency electrodes for generating ion trapping potentials with specified trap locations and curvatures above the electrode plane. A linear-programming algorithm guarantees globally optimal electrode shapes that require only a single radio-frequency voltage source for operation. The optimization method produces final electrode shapes that are smooth and exhibit low fragmentation. Such characteristics are desirable for practical fabrication of surface-electrode trap lattices.
Ion trap is a promising approach to realizing scalable quantum computer as it presents high coherence time. Silicon, due to its manufacturability, is being considered as a potential substrate to fabricate complex ion-trap designs towards trap miniaturization and on-chip integration of electronics and optics. However, Si ion traps need proper structural design to reduce the substrate RF loss. In this paper, high-resistivity Si substrate materials has been utilized to fabricate surface electrode ion trap. Its DC and RF properties has been investigated and compared to the ion trap fabricated on sapphire substrate, which is one of the most established substrate material for trap fabrication.
Abstract We describe the design of a surface-electrode ion trap junction, which is a key element for large-scale ion trap arrays. A bi-objective optimization method is used for designing the electrodes, which maintains the total pseudo-potential curvature while minimizing the axial pseudo-potential gradient along the ion transport path. To facilitate the laser beam delivery for parallel operations in multiple trap zones, we implemented integrated optics on each arm of this X-junction trap. The layout of the trap chip for commercial foundry fabrication is presented. This work suggests routes to improving ion trap junction performance in scalable implementations. Together with integrated optical addressing, this contributes to modular trapped-ion quantum computing in interconnected two-dimensional arrays.