Fault tolerant quantum computation with superconducting elements

Zheng‐Yuan Xue

John P. Preskill

Na Li, Yu-Huai Li, Dao-Jin Fan +7 more

Douglas McClure

Joydip Ghosh, Austin G. Fowler

Superconducting qubits, while promising for scalability and long coherence times, contain more than two energy levels, and therefore are susceptible to errors generated by the leakage of population outside of the computational subspace. Such leakage errors constitute a prominent roadblock towards fault-tolerant quantum computing (FTQC) with superconducting qubits. FTQC using topological codes is based on sequential measurements of multiqubit stabilizer operators. Here, we first propose a leakage-resilient procedure to perform repetitive measurements of multiqubit stabilizer operators, and then use this scheme as an ingredient to develop a leakage-resilient approach for surface code quantum error correction with superconducting circuits. Our protocol is based on swap operations between data and ancilla qubits at the end of every cycle, requiring read-out and reset operations on every physical qubit in the system, and thereby preventing persistent leakage errors from occurring.

Shiro Kawabata

Scaling superconducting quantum computers to the fault-tolerant regime calls for a commensurate scaling of the classical control and readout stack. Today's systems largely rely on room-temperature, rack-based instrumentation connected to dilution-refrigerator cryostats through many coaxial cables. Looking ahead, superconducting fault-tolerant quantum computers (FTQCs) will likely adopt a heterogeneous quantum-classical architecture that places selected electronics at cryogenic stages -- for example, cryo-CMOS at 4~K and superconducting digital logic at 4~K and/or mK stages -- to curb wiring and thermal-load overheads. This review distills key requirements, surveys representative room-temperature and cryogenic approaches, and provides a transparent first-order accounting framework for cryoelectronics. Using an RSA-2048-scale benchmark as a concrete reference point, we illustrate how scaling targets motivate constraints on multiplexing and stage-wise cryogenic power, and discuss implications for functional partitioning across room-temperature electronics, cryo-CMOS, and superconducting logic.