순환 곱 코드의 간단한 두 단계 다수결 논리 디코더 ( A Simplified Two-Step Majority-Logic Decoder for Cyclic Product Codes )

강창언, 정연호

George P. Papoulias

Anouar Yatribi, Mostafa Belkasmi, Fouad Ayoub

Li Guo Zhang, Qin Huang, Shu Lin

Codes constructed based on finite geometries form a large class of cyclic codes with large minimum distances which can be decoded with simple majority-logic decoding in one or multiple steps. In 2001, Kou, Lin and Fossorier showed that the one-step majority-logic decodable finite geometry codes form a class of cyclic LDPC codes whose Tanner graphs are free of cycles of length 4. These cyclic finite geometry LDPC codes perform very well over the AWGN channel using iterative decoding based on belief propagation (IDBP) and have very low error-floors. However, the standard IDBP is not effective for decoding other cyclic finite geometry codes because their Tanner graphs contain too many short cycles of length 4 which severely degrade the decoding performance. This paper investigates iterative decoding of two-step majority-logic decodable finite geometry codes. Three effective algorithms for decoding these codes are proposed. These algorithms are devised based on the orthogonal structure of the parity-check matrices of the codes to avoid or reduce the degrading effect of the short cycles of length 4. These decoding algorithms provide significant coding gains over the standard IDBP using either the sum-product or the min-sum algorithms.

조준호, 성원용

Low-density parity-check (LDPC) 부호의 복호에는 성능이 좋은 합곱 알고리즘(sum-product algorithm; SPA)과 하드웨어가 간단한 비트 반전(bit-flipping; BF) 알고리즘이 많이 쓰이고 있다. 본 논문은 이들 두 가지 방법의 장점을 가지는 저복잡도 고성능 복호 알고리즘을 제안한다. 본 제안된 유연 비트 반전(soft bit-flipping) 알고리즘은 비트와 체크 노드 사이에 전달되는 메시지를 계산하는 데 단순한 비교와 덧셈 연산만을 필요로 하며 연산량이 적다는 장점이 있다. 또한 연산이 완료된 메시지의 활용률을 높이고 비균등 양자화(non-uniform quantization)를 채용하여 1000 내외의 부호 길이에서 SPA 에 0.4dB 근접하는 신호대 잡음비(signal-to-noise ratio)를 달성하였다. 본 논문에서 제안된 알고리즘을 이용하면, 행 무게(row weight)와 열 무게(column weight)가 높아서 종래의 SPA로 구현하기 어려웠던 부호를 비교적 좋은 오율 성능을 유지하면서 실용적으로 구현할 수 있다. ; A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

Hsiu-Chi Chang, Chih-Lung Chen, Hsie-Chia Chang

An {iterative weighted reliability two-step majority logic decoding} (IWRTS-MLGD) algorithm for two-step majority-logic (TS-MLG)-decodable cyclic codes is presented. In contrast to other message passing decoding algorithms that utilize real number operations, our proposed decoding algorithm requires only logical operations and integer additions. Therefore, large computational complexities can be reduced. For moderate-length TS-MLG-decodable cyclic codes, the proposed algorithm aided with soft information and a scaling factor outperforms the hard-decision TS-MLGD algorithm and hard-decision BCH codes with similar length by 1.2- and 1.0-dB, respectively.