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Japanese Journal of Applied Physics

A Large-Scale Packet Switch System and 60-Gbps Pulse Arbitration Circuit Operation Using Single Flux Quantum Technology

Shinichi Yorozu, 義男 亀田, Shuichi Tahara

Published Apr 1, 2001• 0 citations
Publisher

Abstract

We evaluate the performance of a single flux quantum (SFQ) circuit and discuss its possible system-level application. First, we describe an optical-electrical-SFQ hybrid router system that is divided into three functions: an SFQ packet-routing function, a control function, and an optical transmission function. For the packet-switching core, we have developed a packet-switching architecture based on an internal speedup time-shifted Batcher Banyan approach. Our simulated results show that this architecture should provide good scalability and a low packet-loss rate. Additionally, we have fabricated an asynchronous pulse arbitration circuit. This circuit is a key component in our packet-switching system. The circuit synchronizes two asynchronous incoming signals without any global clock signals. It consists of a clock generator based on a ring oscillator and data latches. By measuring the average output voltage of the Josephson junction, we confirmed the output signal control by the clock at over 60 Gbps throughput.

DOI
10.1143/jjap.40.2593

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We evaluate the performance of a single flux quantum (SFQ) circuit and discuss its possible system-level application. First, we describe an optical-electrical-SFQ hybrid router system that is divided into three functions: an SFQ packet-routing function, a control function, and an optical transmission function. For the packet-switching core, we have developed a packet-switching architecture based on an internal speedup time-shifted Batcher Banyan approach. Our simulated results show that this architecture should provide good scalability and a low packet-loss rate. Additionally, we have fabricated an asynchronous pulse arbitration circuit. This circuit is a key component in our packet-switching system. The circuit synchronizes two asynchronous incoming signals without any global clock signals. It consists of a clock generator based on a ring oscillator and data latches. By measuring the average output voltage of the Josephson junction, we confirmed the output signal control by the clock at over 60 Gbps throughput.
We demonstrated the experimental operation of a single flux quantum (SFQ) pulse arbitration circuit for rapid single flux quantum (RSFQ) digital applications. The circuit arbitrates two asynchronous incoming signals with the internal clock signal, and produces two signals with a time difference. The circuit consists of two data latches and a clock generator based on a ring oscillator. We fabricated the circuit using NEC's 2-/spl mu/m standard fabrication technology, and tested it in two ways. Firstly we tested throughput characteristics. From measurements of the average voltage of output Josephson Junctions, we confirmed that the throughput was indeed controlled by the clock signal up to around 60-GHz. Secondly we tested the arbitration function. The test used a new testing circuit connected with output side of the arbitration circuit. This circuit consists of a confluence buffer, a splitter and three SFQ/DCs, and was capable of monitoring output signals and their arrival time difference. We changed the difference in arrival times of the input signals to the arbiter circuit, and observed two output signals with the test circuit. The observed signals show that they always sent out with time difference, and we thus confirmed the correct operation of the circuit even for pairs of input signals with the same arrival time.
We have designed a speedup buffer (SB) that is indispensable for realizing a high-throughput network switch based on single-flux-quantum (SFQ) technology. The SB performs the rate conversion from 10 to 40 Gbps for the packet data streams fed into the Banyan switch. This approach can reduce the packet-blocking rate, resulting in an increased throughput for the network switch. The SB is composed of a 1:3 stream demultiplexer (SDMUX), three variable-bit-length shift registers (VLSRs) and a 3:1 stream multiplexer, coupled with a controller. We have successfully demonstrated the 1:3 SDMUX and the VLSR. As for the VLSR, we confirmed high-speed operation up to 55 GHz. We have also designed the SB using these components. The SB is a large-scale circuit composed of 11 663 Josephson junctions on a 3.8 × 3.8 mm 2 area. So far, partial operations have been demonstrated experimentally.
Large-scale telecommunication systems in nationwide networks will require routers having a packet switching throughput capacity of over several-tens of Tb/s. In such future high-end routers, packet switches will need higher processing speeds than semiconductor devices can provide. We have demonstrated a 40 GHz clock, 0.8 mW, 160 Gb/s, 4/spl times/4 switch circuit that uses single flux quantum (SFQ) technology. The main components of an SFQ circuit are Josephson junctions and a superconducting loop. In designing the circuit, we have developed two key technologies: an automatic cell placement and route tool to increase designable circuit scale; a passive interconnection to decrease latency. These technologies will enable implementing Tb/s-scale switches and switch schedulers for high-speed packet switching systems.
Large-scale telecommunication systems in the larger nationwide network of the next decade will require routers having a packet switching throughput capacity of over several-tens Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. In this paper, we describe an SFQ packet switch architecture that is used in the internal speed-up Banyan network. According to the architecture we have designed and demonstrated a deep-pipelined 2/spl times/2 packet switch logic circuit, which is the key element in a packet switch, by applying two technological advances regarding design methodology and packaging. This circuit is among the largest SFQ random logic circuits yet reported.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
We are developing a single-flux-quantum (SFQ) packet switch for over 1-Tb/s switching systems. Investigation of several switch topologies leads us to select the Batcher-Banyan packet switch because of its simplicity and regularity. The packet switch structure we propose consists of simple 2/spl times/2 unit switches each connected by speeded-up internal links. Numeric simulation showed that the speeded-up links greatly improved the throughput by resolving packet blocking, which is a major drawback of the Banyan switch. High throughput compatible to a crossbar switch was attained by using links whose speed was quadrupled. Moreover, the throughput did not decrease even though the number of input/output ports increased. Taking the speed of SFQ basic gates into account, the cycle time of the 2/spl times/2 unit switch reaches 25 ps, which is sufficient to achieve the 40-GHz operation. If unit switches are connected by quadrupled internal links, the Batcher-Banyan switch can accept the 10-Gb/s external input rate per channel. This indicates that the total throughput of a 128/spl times/128 switch exceeds 1 Tb/s. The unit switch was designed down to the SFQ gate level. To design a large SFQ circuit, we built several "standard" SFQ cells whose shape was square or rectangular with a unit width and height. Such shapes make it easier to place and connect a number of cells. We show some experimental results of testing SFQ standard cells and logic circuits.