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International Conference on Signal Processing and Communication Systems

A low-complexity high-performance decoding algorithm for fixed-point LDPC decoders

Jui-Hui Hung, Sau-Gee Chen

Published Dec 1, 2008• 2 citations
Publisher

Abstract

The bit-error-rate (BER) performance of an LDPC decoding algorithm will be seriously degraded when the algorithm is realized with fixed-point implementation in practical applications, due to the introduced quantization errors and rounding errors. To remedy the problem, this paper proposes an improved min-sum algorithm (MSA), called CMVP algorithm. It achieves better performances than the popular min-sum algorithm (MSA), under the condition of the same fixed-point precision. Besides, the hardware overhead of the new algorithm over conventional MSA is small. On the other hand, under the condition of comparable performances, MSA algorithm needs a higher fixed-point precision and hardware costs than the new CMVP algorithm, according to the simulations and hardware synthesis results. The new algorithm also works well in a wide range of code rates and code lengths.

DOI
10.1109/icspcs.2008.4813725

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The bit-error-rate (BER) performance of an LDPC decoding algorithm will be seriously degraded when the algorithm is realized with fixed-point implementation in practical applications, due to the introduced quantization errors and rounding errors. To remedy the problem, this paper proposes an improved min-sum algorithm (MSA), called CMVP algorithm. It achieves better performances than the popular min-sum algorithm (MSA), under the condition of the same fixed-point precision. Besides, the hardware overhead of the new algorithm over conventional MSA is small. On the other hand, under the condition of comparable performances, MSA algorithm needs a higher fixed-point precision and hardware costs than the new CMVP algorithm, according to the simulations and hardware synthesis results. The new algorithm also works well in a wide range of code rates and code lengths.
Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.
This letter proposes a new algorithm for the check node update in the decoding of low-density parity-check (LDPC) codes. The proposed algorithm is based on a new approximation formula of standard sum-product algorithm (SPA) which can reduce the approximation error of min-sum algorithm (MSA) and has almost the same performance as sum-product algorithm (SPA) under both floating precision operation and fixed-point operation. Besides, the new approximation formula can be implemented in simple structures competitive with MSA.
In this work, a high performance LDPC decoder architecture is presented. It is a partially-parallel architecture for low-complexity consideration. In order to eliminate the idling time and hardware complexity in conventional partially-parallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the parity-check matrix is optimally partitioned into four unequal sub-matrices that lead to high efficiency in hardware sharing. As a result, it can handle two different codewords simultaneously with 100% hardware utilization. Furthermore, for minimizing the performance loss due to round-off errors in fixed-point implementations, the well-known modified min-sum decoding algorithm is enhanced by our recently proposed high-performance CMVP decoding algorithm. Overall, the proposed decoder has high throughput, low complexity, and good BER performances. In the circuit implementation example of the (576, 288) parity check matrix for IEEE 802.16e standard, the decoder achieves a data rate of 5.5Gbps assuming 10 decoding iterations and 7 quantization bits, with a small area of 653K gates, based on UMC 90nm process technology.
Compared with the sum-product algorithm (SPA) with high decoding complexity for low-density parity-check (LDPC) codes, its approximated version, the min-sum algorithm (MSA), reduces the computational complexity at the cost of slight performance degradation. In order to compensate the oversized check-node messages in the MSA, the effect of clipping on variable-node messages is investigated under two-bit resolution. Our results show that the performance of clipped MSA degrades at the high bit error rate (BER) and increases at the low BER as clipping threshold enlarges. Based on these results, we propose a modified quantized MS decoding algorithm where the adaptive clipping threshold is applied on the variable-node messages according to the number of unsatisfied checks per-iteration. The adaptive rule is designed for easy hardware implementations. Numerical results show that the proposed algorithm has considerable improvement in performance compared with the MSA under two-bit precision. And it can achieve the performance near the SPA for some short-length LDPC codes.
It is well known that for decoding low-density parity-check (LDPC) codes, the attenuated min-sum algorithm (AMSA) and the offset min-sum algorithm (OMSA) can outperform the conventional min-sum algorithm (MSA) at low signal-to-noise-ratios (SNRs). In this paper, we demonstrate that, for quantized LDPC decoders, although the MSA achieves better high SNR performance than the AMSA and OMSA, each of the MSA, AMSA, and OMSA all suffer from a relatively high error floor. Therefore, we propose a novel modification of the MSA for decoding quantized LDPC codes with the aim of lowering the error floor. Compared to the quantized MSA, the proposed modification is also helpful at low SNRs, where it matches the waterfall performance of the quantized AMSA and OMSA. The new algorithm is designed based on the assumption that trapping/absorbing sets (or other problematic graphical objects) are the major cause of the error floor for quantized LDPC decoders, and it aims to reduce the probability that these problematic objects lead to decoding errors.
In this paper, we analyze the performance of quantized offset min-sum (MS) decoding algorithm and propose an optimally quantized offset MS algorithm for a flexible low-density parity-check (LDPC) decoder. It is known that the offset MS decoding algorithm is implemented with simplified hardware complexity and achieves good decoding performance. However, the finite precision effects in decoding LDPC codes result in performance different from floating point. The performance degradation is caused by different dynamic ranges of input data at high signal-to-noise ratio (SNR). The proposed offset MS algorithm uses the received data directly instead of log-likelihood ratio (LLR) data as the intrinsic information. It can achieve better performance than the conventional one since its offset factor is more effective at a wide range of SNR and the intrinsic information is quantized more robustly since it is independent of channel information. Also, it is possible for the proposed scheme to use a same quantization scheme for a flexible LDPC decoder, which can decode several kinds of LDPC codes. Simulation results show that our optimally quantized offset MS algorithms with 5-bits for (1728, 864) and (1728, 1296) irregular LDPC codes achieve better performance compared with the conventional offset MS algorithms with 6-bits quantization scheme.