Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Physical Review A

Programmable architecture for quantum computing

Jialin Chen, Lingli Wang, Edoardo Charbon A, Bin Wang

Published Aug 9, 2013• 10 citations
Publisher

Abstract

A programmable architecture called ``quantum FPGA (field-programmable gate array)'' (QFPGA) is presented for quantum computing, which is a hybrid model combining the advantages of the qubus system and the measurement-based quantum computation. There are two kinds of buses in QFPGA, the local bus and the global bus, which generate the cluster states and general multiqubit rotations around the $z$ axis, respectively. QFPGA consists of quantum logic blocks (QLBs) and quantum routing channels (QRCs). The QLB is used to generate a small quantum logic while the QRC is used to combine them properly for larger logic realization. Considering the error accumulating on the qubus, the small logic is the general two-qubit quantum gate. However, for the application such as $n$-qubit quantum Fourier transform, one QLB can be reconfigured for four-qubit quantum Fourier transform. Although this is an implementation-independent architecture, we still make a rough analysis of its performance based on the qubus system. In a word, QFPGA provides a general architecture to integrate different quantum computing models for efficient quantum logic construction.

DOI
10.1103/physreva.88.022311

Related papers

Quantum FPGA architecture design

Jialin Chen, Lingli Wang, Bin Wang

A Quantum FPGA (QFPGA) architecture is presented for programmable quantum computing, which is a hybrid architecture combining the advantages of the measurement-based quantum computation and the qubus system. QFPGA consists of Quantum Logic Blocks (QLBs) and Quantum Routing Channels (QRCs). The QLB is used to realize a small quantum logic while the QRC is to combine them properly for larger logic realization. There are two types of buses in QFPGA, the local bus in the QLB and the global bus in the QRC, which are to generate the cluster states and general multiqubit rotations around the z axis respectively. However for some applications such as Grover's algorithm and n-qubit quantum Fourier transform, one QLB can be configured for four-qubit phase shift module and four-qubit quantum Fourier transform respectively.

International Conference on Field-Programmable Technology (FPT)•Dec 1, 2013•6 citations

FPGA-based quantum circuit emulation: A case study on Quantum Fourier transform

Y. H. Lee, Mohamed Khalil-Hani, Muhammad Nadzir Marsono

Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.

International Symposium on Integrated Circuits•Dec 1, 2014•6 citations

A Scalable FPGA Architecture for Quantum Computing Simulation

Lee A. Belfore

A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).

arXiv:2407.06415•Jul 8, 2024•0 citations

FPGA Based Quantum Circuit Simulator: Processing 30 Qubit Systems

Nasir Ali Nasir Ali, Anupam Tiwari, Nadeem khan Nadeem khan +5 more

Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.

•Jan 20, 2026•1 citation

FPGA Based Digital Quantum Computer Verification

Valerii Hlukhov

Quantum computers are analog and probabilistic computers and, in fact, they play the role of coprocessors in relation to classical computers. The components of quantum coprocessors are called qubits. Their behavior should be described by a wave function. In particular, qubits can be discrete objects - finite states machines. Such qubits will be called digital. Quantum coprocessors and quantum computers built on their basis will also be called digital. External influences on digital qubits are fed through digital quantum gates. So a digital qubit is a unique chain of digital quantum gates. Digital quantum coprocessor can be implemented in FPGA as several chains of digital quantum.The article explores FPGA-based digital quantum coprocessor. It consists of 32 qubits. The structures of digital quantum gates, digital qubits, and a digital quantum coprocessor capable of performing the quantum Fourier transform are presented. Digital qubits were implemented for the case of real amplitudes of the wave functions.The results of the quantum Fourier transform of a 32-qubit digital quantum coprocessor implemented on one FPGA are presented.The execution time of one quantum Fourier transform does not depend on the number of qubits in the digital quantum coprocessor and is commensurate with the time of electron spin change (near 10 ns). But the time complexity of the quantum Fourier transform is probabilistic polynomial in time. The measured ratio of correct results for a 32-qubit coprocessor is approximately 1700 ppm.

International Conference on Dependable Systems, Services and Technologies (DESSERT)•May 1, 2020•8 citations

Quantum computing modelling on field programmable gate array based on state vector and heisenberg models

Yee Hui Lee

As current trend of miniaturization in computing technology continues, modern computing devices would start to exhibit the behaviour of nanoscopic quantum objects. Quantum computing, which is based on the principles of quantum mechanics, becomes a promising candidate for future generation computing system. However, modelling quantum computing systems on existing classical computing platforms before the realization of viable large-scale quantum computer remains a major challenge. The exploration on the modelling of quantum computing systems on field programmable gate array (FPGA) platform, which offers the potential of massive parallelism and allows computational optimization at register-transfer level, is crucial. Due to the exponential growth of resource utilization with the increase in the number of quantum bits (qubit), existing works on modelling of quantum systems on FPGA platform are restricted to simple case studies using small qubit sizes. This work explores the modelling of quantum computing for emulation on FPGA platform based on two types of data structure: (a) state vector model and (b) Heisenberg model. For the conventional state vector modelling approach, an efficient datapath design that is based on serial-parallel hardware architecture, which allows resource sharing between unitary transformations, is proposed. Heisenberg model has been proven to be efficient in modelling stabilizer circuits, which are critical in error correction operations. In the effort to include the consideration of vital quantum error correction in practical quantum systems, a novel FPGA emulation framework that is based on the Heisenberg model is proposed. Effective algorithms for accurate global phase maintenance are proposed to facilitate the modelling of quantum systems based on the Heisenberg representation. The feasibility of the proposed state vector and Heisenberg emulation models are demonstrated based on a number of case studies with different characteristics, which include quantum Fourier transform, Grover’s search algorithm, and stabilizer circuits. Based on the state vector approach, this work has demonstrated the advantage of FPGA emulation over software simulation where hardware emulation of 7-qubit Grover’s search is about 3 × 104 times faster than the software simulation performed on Intel Core i7-4790 processor running at 3.6GHz clock rate. In contrast to the 8-qubit implementation based on the state vector model, the proposed FPGA emulation framework based on the Heisenberg model has successfully modelled 120-qubit stabilizer circuits on the Altera Stratix IV FPGA. In summary, the proposed work in this thesis contributes to the formulation of a proof-of-concept of efficient FPGA emulation framework based on the state vector and Heisenberg models.

•Mar 1, 2017•0 citations
A programmable architecture called ``quantum FPGA (field-programmable gate array)'' (QFPGA) is presented for quantum computing, which is a hybrid model combining the advantages of the qubus system and the measurement-based quantum computation. There are two kinds of buses in QFPGA, the local bus and the global bus, which generate the cluster states and general multiqubit rotations around the zzz axis, respectively. QFPGA consists of quantum logic blocks (QLBs) and quantum routing channels (QRCs). The QLB is used to generate a small quantum logic while the QRC is used to combine them properly for larger logic realization. Considering the error accumulating on the qubus, the small logic is the general two-qubit quantum gate. However, for the application such as nnn-qubit quantum Fourier transform, one QLB can be reconfigured for four-qubit quantum Fourier transform. Although this is an implementation-independent architecture, we still make a rough analysis of its performance based on the qubus system. In a word, QFPGA provides a general architecture to integrate different quantum computing models for efficient quantum logic construction.
A Quantum FPGA (QFPGA) architecture is presented for programmable quantum computing, which is a hybrid architecture combining the advantages of the measurement-based quantum computation and the qubus system. QFPGA consists of Quantum Logic Blocks (QLBs) and Quantum Routing Channels (QRCs). The QLB is used to realize a small quantum logic while the QRC is to combine them properly for larger logic realization. There are two types of buses in QFPGA, the local bus in the QLB and the global bus in the QRC, which are to generate the cluster states and general multiqubit rotations around the z axis respectively. However for some applications such as Grover's algorithm and n-qubit quantum Fourier transform, one QLB can be configured for four-qubit phase shift module and four-qubit quantum Fourier transform respectively.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.
A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Quantum computers are analog and probabilistic computers and, in fact, they play the role of coprocessors in relation to classical computers. The components of quantum coprocessors are called qubits. Their behavior should be described by a wave function. In particular, qubits can be discrete objects - finite states machines. Such qubits will be called digital. Quantum coprocessors and quantum computers built on their basis will also be called digital. External influences on digital qubits are fed through digital quantum gates. So a digital qubit is a unique chain of digital quantum gates. Digital quantum coprocessor can be implemented in FPGA as several chains of digital quantum.The article explores FPGA-based digital quantum coprocessor. It consists of 32 qubits. The structures of digital quantum gates, digital qubits, and a digital quantum coprocessor capable of performing the quantum Fourier transform are presented. Digital qubits were implemented for the case of real amplitudes of the wave functions.The results of the quantum Fourier transform of a 32-qubit digital quantum coprocessor implemented on one FPGA are presented.The execution time of one quantum Fourier transform does not depend on the number of qubits in the digital quantum coprocessor and is commensurate with the time of electron spin change (near 10 ns). But the time complexity of the quantum Fourier transform is probabilistic polynomial in time. The measured ratio of correct results for a 32-qubit coprocessor is approximately 1700 ppm.
As current trend of miniaturization in computing technology continues, modern computing devices would start to exhibit the behaviour of nanoscopic quantum objects. Quantum computing, which is based on the principles of quantum mechanics, becomes a promising candidate for future generation computing system. However, modelling quantum computing systems on existing classical computing platforms before the realization of viable large-scale quantum computer remains a major challenge. The exploration on the modelling of quantum computing systems on field programmable gate array (FPGA) platform, which offers the potential of massive parallelism and allows computational optimization at register-transfer level, is crucial. Due to the exponential growth of resource utilization with the increase in the number of quantum bits (qubit), existing works on modelling of quantum systems on FPGA platform are restricted to simple case studies using small qubit sizes. This work explores the modelling of quantum computing for emulation on FPGA platform based on two types of data structure: (a) state vector model and (b) Heisenberg model. For the conventional state vector modelling approach, an efficient datapath design that is based on serial-parallel hardware architecture, which allows resource sharing between unitary transformations, is proposed. Heisenberg model has been proven to be efficient in modelling stabilizer circuits, which are critical in error correction operations. In the effort to include the consideration of vital quantum error correction in practical quantum systems, a novel FPGA emulation framework that is based on the Heisenberg model is proposed. Effective algorithms for accurate global phase maintenance are proposed to facilitate the modelling of quantum systems based on the Heisenberg representation. The feasibility of the proposed state vector and Heisenberg emulation models are demonstrated based on a number of case studies with different characteristics, which include quantum Fourier transform, Grover’s search algorithm, and stabilizer circuits. Based on the state vector approach, this work has demonstrated the advantage of FPGA emulation over software simulation where hardware emulation of 7-qubit Grover’s search is about 3 × 104 times faster than the software simulation performed on Intel Core i7-4790 processor running at 3.6GHz clock rate. In contrast to the 8-qubit implementation based on the state vector model, the proposed FPGA emulation framework based on the Heisenberg model has successfully modelled 120-qubit stabilizer circuits on the Altera Stratix IV FPGA. In summary, the proposed work in this thesis contributes to the formulation of a proof-of-concept of efficient FPGA emulation framework based on the state vector and Heisenberg models.