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IEEE Transactions on Microwave Theory and Techniques

Cryogenic microwave channelized receiver

C. Rauscher, J.M. Pond, Gregory B. Tait

Published Jul 1, 1996• 11 citations
Publisher

Abstract

The channelized receiver being presented demonstrates the use of high temperature superconductor technology in a microwave system setting where superconductor, microwave-monolithic-integrated-circuit and hybrid-integrated-circuit components are united in one package and cooled to liquid-nitrogen temperatures. The receiver consists of a superconducting X-band four-channel demultiplexer with 100-MHz-wide channels, four commercial monolithically integrated mixers, and four custom-designed hybrid-circuit detectors containing heterostructure ramp diodes. The composite receiver unit has been integrated into the payload of the second-phase NRL high temperature superconductor space experiment (HTSSE-II). Prior to payload assembly, the response characteristics of the receiver were measured as functions of frequency, temperature, and drive levels. The article describes the circuitry, discusses the key issues related to design and implementation, and summarizes the experimental results.

DOI
10.1109/22.508229

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•Mar 1, 2021•1 citation
The channelized receiver being presented demonstrates the use of high temperature superconductor technology in a microwave system setting where superconductor, microwave-monolithic-integrated-circuit and hybrid-integrated-circuit components are united in one package and cooled to liquid-nitrogen temperatures. The receiver consists of a superconducting X-band four-channel demultiplexer with 100-MHz-wide channels, four commercial monolithically integrated mixers, and four custom-designed hybrid-circuit detectors containing heterostructure ramp diodes. The composite receiver unit has been integrated into the payload of the second-phase NRL high temperature superconductor space experiment (HTSSE-II). Prior to payload assembly, the response characteristics of the receiver were measured as functions of frequency, temperature, and drive levels. The article describes the circuitry, discusses the key issues related to design and implementation, and summarizes the experimental results.
Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.
A 6 GHz hybrid superconductive/semiconductive microwave receiver (HSSMR) has been developed. It consists of an HTS microstrip preselect filter, a cryogenic LNA, a commercially available off-the-shelf mixer, and a superconducting local oscillator (LO). The operating bandwidth is 500 MHz, which is centered at an RF frequency of 5.9 GHz and a corresponding IF frequency of 4.483 GHz. Downconversion is facilitated by a 10.383 GHz LO. The oscillator incorporates an HTS/sapphire resonator with a measured unloaded Q of 98100, at 77 K. The entire receiver is cooled to an operating temperature of 77 K. The measured performance is given for each of the components and for the overall receiver. The resultant receiver conversion gain is 27.5 dB and the associated noise figure is less than 0.7 dB.
New superconducting element, a cryogenic phase detector (CPD) has been proposed and preliminary tested. The CPD is based on a superconductor-insulator-superconductor junction and initially intended for phase locking of a flux-flow oscillator in a superconducting integrated receiver. First results of the CPD development and study are very encouraging; a sinusoidal response of the CPD has been measured at the variation of the phase shift between input signals. Dependences of the output signal and phase response on the CPD bias voltage have been studied; main parameters of this new device are estimated. Important that the CPD output current well above 10 has been measured at the input signal provided by the harmonic mixer of the integrated receiver and amplified by the existing HEMT-amplifier. Due to the large conversion coefficient this current being supplied to the flux-flow oscillator (FFO) control line is sufficient to directly tune FFO frequency. Obtained data demonstrate that the CPD intrinsically could operate with effective bandwidth more than 100 MHz. Preliminary results of the CPD implementation for the FFO phase locking are presented; possible advantages of such combination are discussed.
We have developed a cryogenic probe and cryostat system to test both active and passive superconducting devices and circuits up to microwave frequencies at variable temperatures. Our system consists of two basic parts: the cryostat and the matching probe. The cryostat is a unique, very efficient, variable temperature, flow-type cryostat, where we control temperature without electrical heaters. It is magnetically shielded and allows rapid testing between 4.2 K and room temperature. Probes developed for this cryostat have a larger number of shorter cables than standard dip-type probes. They are designed to test chips or chip assemblies without additional packaging. Chips or chip assemblies can be quickly mounted and dismounted from a fixed spring-contact assembly. Each probe has 56 wide-bandwidth signal cables. We have repeatedly used these probes for testing both active and passive superconducting integrated circuits up to 20 GHz. The probe and cryostat combination provides a testing capability that is simultaneously high frequency, dc magnetic shielded, has variable cryogenic temperature, and quick turnaround.
Abstract : Superconductor-Insulator-Superconductor (SIS) tunnel junction mixers are known to provide ultra-high sensitivity receiver applications above 30 GHz. In this two year (Phase II) program, HYPRES, in collaboration with the National Radio Astronomy Observatory, have developed novel fully integrated SIS mixer circuits, and demonstrated a unique high efficiency cooling system. The integrated SIS mixer chip contains, aside from the actual mixer elements, passive tuning components, an IF filter, a coplanar transmission line, and a waveguide coupler, necessary components heretofore realized off-chip. Fabrication of the integrated mixer required development of a nine level process and optimization of the process dependent electrical parameters of the SIS devices. The device performs efficiently in the range of 75-115 GHz. A novel dewar-based cooler, which makes use of the extremely low thermal conductivity of the fused silica chip substrate to achieve an incremental thermal load of 25 mW, was fabricated and demonstrated. Such a cryostat allows relatively long term unattended operation of SIS, or other, cryogenic devices.
This thesis proposes a pathway to realizing large-scale quantum computing integrated circuits based on the monolithic integration of high-temperature (1–4 K) semiconductor qubits with their associated control and readout circuitry. High-frequency device characterization was performed on production 22-nm FDSOI technology at room and cryogenic temperatures (down to 3.3 K) to inform a cryogenic circuit design methodology in the absence of low-temperature device models. The methodology was demonstrated with a TIA qubit-readout chain that was, for the first time, monolithically integrated with electron and hole quantum dot structures. The prospects of FDSOI SiGe BiCMOS technology would enable similar integration with higher performance HBT devices. As a first step, design of a 240-GHz direct conversion I-Q receiver is showcased in 55-nm SiGe BiCMOS, intended for frequency-division multiplexed readout of many qubits. The measured IF-bandwidth of 59 GHz makes it suitable for high data-rate communication and large-scale quantum processors.