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IEEE Transactions on Applied Superconductivity

NbN and Nb SFQ device performance

Mark W. Johnson, Bruce J. Dalrymple, D.J. Durand, Jerome A. Luine

Published Jun 1, 2003• 3 citations
Publisher

Abstract

The static frequency divider is commonly used as a performance benchmark for both superconductor and semiconductor digital device technologies. We present results of a static divide-by-two circuit, an NbN (1 kA/cm/sup 2/) SFQ T-flip-flop (TFF) operating to 97 GHz. Details of the measurement and operating criterion are discussed. Measurements of junction capacitance, a particularly important factor effecting device performance, are presented for TRW's NbN process. Simulations of expected device performance are shown to explain measured performance reasonably well. NbN results are presented alongside a those of a recent 8kA/cm/sup 2/ Nb divider operating at 300 GHz, as well as published Nb TFF results.

DOI
10.1109/tasc.2003.813949

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The static frequency divider is commonly used as a performance benchmark for both superconductor and semiconductor digital device technologies. We present results of a static divide-by-two circuit, an NbN (1 kA/cm/sup 2/) SFQ T-flip-flop (TFF) operating to 97 GHz. Details of the measurement and operating criterion are discussed. Measurements of junction capacitance, a particularly important factor effecting device performance, are presented for TRW's NbN process. Simulations of expected device performance are shown to explain measured performance reasonably well. NbN results are presented alongside a those of a recent 8kA/cm/sup 2/ Nb divider operating at 300 GHz, as well as published Nb TFF results.
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Abstract We performed a comprehensive investigation of the relationship between the maximum operating frequency of the NbN superconducting frequency divider and the key parameters of the NbN Josephson junction (JJ). We designed a superconducting frequency divider that uses a single NbN JJ as a pulse generator, several NbN Josephson transmission lines, an NbN Toggle Flip-flop, and a load. By comparing the bias voltage V in of the pulse generator with the output voltage V out of the load, we determined if the circuit was working correctly and calculated the maximum operating frequency f max. Additionally, we employed JSICsim software for simulations to analyze the impact of key parameters of the NbN JJ, such as critical current density J c, gap voltage V g, characteristic voltage V c, quality factor Q, and specific capacitance C s, on f max. The simulation results demonstrate that f max increases with increasing J c and Q. Specifically when J c exceeds 300 kA cm−2 and Q surpasses 4, the superconducting frequency divider can achieve a f max of 1 THz. Furthermore, we successfully fabricated a superconducting frequency divider using a 10 kA cm−2 process and tested a f max of 260 GHz, with a deviation of approximately 6% from the simulation results.
Rapid Single Flux Quantum (RSFQ) T-flip flops (TFFs) operating up to 770 GHz have been demonstrated at 4.2 K. The devices, consisting of either resistively shunted or unshunted Josephson junctions, are fabricated using a planarized Nb/AlO/sub x//Nb trilayer process. Electron beam lithography is used to pattern all levels with a minimum junction area less than 0.1 /spl mu/m/sup 2/. Critical current densities of 0.5 mA//spl mu/m/sup 2/ and 2.5 mA//spl mu/m/sup 2/ are used for the shunted (tested at 1.8 K) and unshunted devices (tested at 4.2 K) respectively. The input and output frequencies of the TFFs are obtained from the input and output voltages by the Josephson relation. The output voltage is exactly half of the input voltage when the divide-by-two operation is correct.
We investigated high-current-density Josephson junctions with NbxSi1-xbarriers in single-flux-quantum (SFQ) digital circuits to evaluate their performance at clock frequencies of hundreds of gigahertz. We fabricated static divider SFQ circuits with a-NbxSi1-xand a-Si barriers for Jcranging from 3.5 to 85 kA/cm2. For junctions in the lower Jcrange (3.5-17 kA/cm2), we used optical lithography, and for the 85-kA/cm2junctions, we used electron-beam lithography. We measured SFQ circuits with a maximum operating speed of 300 GHz by use of intrinsically shunted junctions having submicrometer dimensions and an 85-kA/cm2critical current density. These results demonstrate that silicide-barrier junctions have the potential to achieve high-speed SFQ circuits and high-density circuits because the junctions are small and do not require external shunt resistors.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.