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IEEE Transactions on Applied Superconductivity

Operation of a superconductive demultiplexer using rapid single flux quantum (RSFQ) technology

Steven B. Kaplan, Oleg A. Mukhanov

Published Jun 1, 1995• 25 citations
Publisher

Abstract

A superconductive demultiplexer was designed, simulated, and tested as an interface between ultra-fast superconductive circuits and slower room-temperature electronics. The modular RSFQ shift-and-dump circuit was designed as a register of Non-Destructive Read-Out (NDRO) cells, which are timed by pulses from the system clock. Data is read out from a 1:N demultiplexer every N clock periods by applying a read-out pulse to the register's NDRO input. Circuit simulations and results for the successful experimental test of a 2-stage demultiplexer will be discussed.>

DOI
10.1109/77.403186

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IEEE Transactions on Applied Superconductivity•Jan 1, 1992•21 citations
A superconductive demultiplexer was designed, simulated, and tested as an interface between ultra-fast superconductive circuits and slower room-temperature electronics. The modular RSFQ shift-and-dump circuit was designed as a register of Non-Destructive Read-Out (NDRO) cells, which are timed by pulses from the system clock. Data is read out from a 1:N demultiplexer every N clock periods by applying a read-out pulse to the register's NDRO input. Circuit simulations and results for the successful experimental test of a 2-stage demultiplexer will be discussed.>
A demultiplexer (DMUX) is a key subsystem of rapid single flux quantum (RSFQ) circuits and systems in practical applications. High-speed data from RSFQ circuits should be converted into sufficiently low-speed ones for transmission to and processing by room temperature electronics. We designed, fabricated and successfully tested an RSFQ DMUX based on the synchronous shift-and-dump architecture whose advantages are modularity and compactness. A 1-to-8 DMUX was implemented using our standard cell library on 1.6 kA cm −2 Nb trilayer technology. Fully functional operation was confirmed by low speed testing. Experimental bias margins were as large as ±16%. Results of average voltage measurements implied that the DMUX was operated at data rates up to 25 Gb s −1 .
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>
We describe the design of a fast single-flux-quantum decoder which can be used, e.g., in fast RAMs, general-purpose microprocessors, and communication channel switches. The core of the circuit is a tree of the single-bit SFQ demultiplexer with toggle (rather than the reset-set) control. Three new RSFQ cells: the demultiplexer, D flip-flop with complementary outputs, and serial XOR with large parameter tolerances (dc bias margins of /spl plusmn/25%, /spl plusmn/26%, and /spl plusmn/27%, respectively) have been developed for the decoder project. We have designed the first 16-bit prototype of the decoder for 1-kA/cm/sup 2/ niobium-trilayer technology and tested it at low frequencies. The circuit was completely operable except for 3 (of 16) output SFQ/DC converters. Simulations show that the circuit should allow data rate in excess of 60 Gbit/s and channel switching time below 20 ps.>
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>