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Asilomar Conference on Signals, Systems and Computers (ACSSC)

A thresholding algorithm for improved Split-Row decoding of LDPC codes

Tinoosh Mohsenin, Pascal Urard, Bevan M. Baas

Published Oct 1, 2008• 7 citations
Publisher

Abstract

The recently proposed split-row decoding algorithm provides significant improvements in the throughput, hardware efficiency and energy efficiency when compared to existing soft decision decoding algorithms at the cost of some error performance loss. In this paper we propose split-row threshold which outperforms the split-row algorithm while maintaining the same level of complexity. Simulation results show that the algorithm provides 0.15-0.2 dB coding gain over split-row decoding and is within 0.15-0.2 dB of SPA and MinSum normalized.

DOI
10.1109/acssc.2008.5074444

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Information•Nov 1, 2024•1 citation
The recently proposed split-row decoding algorithm provides significant improvements in the throughput, hardware efficiency and energy efficiency when compared to existing soft decision decoding algorithms at the cost of some error performance loss. In this paper we propose split-row threshold which outperforms the split-row algorithm while maintaining the same level of complexity. Simulation results show that the algorithm provides 0.15-0.2 dB coding gain over split-row decoding and is within 0.15-0.2 dB of SPA and MinSum normalized.
In this paper, we propose a thresholding algorithm to improve Split-Row decoding method of irregular LDPC codes, with maintaining the same level of complexity. We present in this paper a full description of this method and its benefits for various row weight and length code word. In this context, we have performed an implementation on MATLAB of an irregular LDPC codes with different code word and code rate. Simulation results over an additive white Gaussian channel show that the error performance of high row-weight codes with thresholding algorithm is within 0.1–0.2 dB of the normalized Min-Sum algorithm. The study result shows that the thresholding algorithm outperforms original Split Row of irregular codes.
A reduced complexity LDPC decoding method for regular LDPC code is extended to irregular LDPC codes; we present in this paper a full description of this method and its benefits for various row weight and length code word. The Split-Row method makes column processing parallelism easier to exploit and significantly simplifies row processors. Simulation results over an additive white Gaussian channel show that the error performance of high row-weight codes with Split-Row decoding is within 0.3-0.5 dB of the Min-Sum algorithm.
In this paper, we have proposed a novel method of decoding algorithm of irregular LDPC codes. A reduced complexity LDPC decoding method for regular LDPC code is extended to irregular LDPC codes. We present in this paper a full description of this method and its benefits for various row weight and length code word. The Split-Row method makes column processing parallelism easier to exploit and significantly simplifies row processors. Recently, irregular LDPC codes have received a lot of attention by many advanced standard, such as WiFi, WiMAX Mobile and digital video broadcasting (DVB-S2). Hence the idea to develop the “Split-Row Method” for irregular LDPC codes. In this context, we have performed an implementation on MATLAB of an irregular LDPC codes with different code word and code rate; simulation results over an additive white Gaussian channel show that the error performance of high row-weight codes with Split-Row decoding is within 0.3–0.5 dB of the Min-Sum algorithm. The study result shows that the “Split Row Method” is better for irregular code than regular LDPC codes.
We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10−5 with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps.