IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Security Processor with Quantum Key Distribution
Thomas Lorünser, Edwin Querasser, Thomas Matyus, Momtchil Peev, Johannes Wolkerstorfer, Michael Hutter, Alexander Szekely, Ilse Wimberger, Christian Pfaffel-Janser, Andreas Neppach
We present a fully operable security gateway prototype, integrating quantum key distribution and realised as a system-on-chip. It is implemented on a field-programmable gate array and provides a virtual private network with low latency and gigabit throughput. The seamless hard- and software integration of a quantum key distribution layer enables high key-update rates for the encryption modules. Hence, the amount of data encrypted with one session key can be significantly decreased. We realise a highly modular architecture and make extensive use of software/hardware partitioning. This work is the first approach towards application of a new key distribution technology in dedicated security processors. In particular, it elaborates requirements for the integration of quantum key distribution on a chip level.
We present a fully operable security gateway prototype, integrating quantum key distribution and realised as a system-on-chip. It is implemented on a field-programmable gate array and provides a virtual private network with low latency and gigabit throughput. The seamless hard- and software integration of a quantum key distribution layer enables high key-update rates for the encryption modules. Hence, the amount of data encrypted with one session key can be significantly decreased. We realise a highly modular architecture and make extensive use of software/hardware partitioning. This work is the first approach towards application of a new key distribution technology in dedicated security processors. In particular, it elaborates requirements for the integration of quantum key distribution on a chip level.
This paper presents a key management approach for quantum generated keys and its integration into the IPsec/IKE protocol. The solution is used in a security gateway that integrates quantum key distribution (QKD) and IPsec as a system-on-chip solution. The QKD acquisition module and the IPsec part of this prototype are implemented in hardware to provide a high level of integration as well as high encryption throughput. To make use of these fast encryption capabilities, a flexible key management approach is necessary to provide keys just in time. Thus, the presented key management approach focuses on an efficient key update mechanism and minimizes the communication overhead. Furthermore, the presented approach is a first step to integrate QKD solutions into
real-world commercial applications using standardized interfaces.
Abstract This paper presents a new hardware implementation of the quantum key distributed cryptography protocol using Field Programmable Gate Array (FPGA). In many security applications, the software implementations of key distribution algorithms are slow and inefficient. In order to solve this problems, new hardware architecture was proposed to speed up the performance and flexibility of key distribution algorithms. The concurrent computing designs quantum key distribution protocol with reducing the hardware area, producing a high throughput and low latency. It also showed high speed processing and consumed low power. An efficient hardware architectural model for quantum key distribution protocol was developed using very high-speed integrated circuit hardware description language (VHDL). This hardware designed to be used with any quantum key distribution protocol to distribution the secret key securely. The hardware implemented and test with Spartan-3 FPGA board and the results show a throughput of 8 Mbps and efficiency of 1.6 Mbps/slice.
Quantum key distribution (QKD) provides a secure and effective way of exchanging cryptographic symmetric keys without the possibility of an eavesdropper being undetected. The transmission and detection of the quantum states at the physical layer is the first step to defining a common source of entropy, where both parties will extract a raw key. Over the last few years, continuous variable quantum key distribution (CV-QKD) protocols have become an attractive technology for QKD, providing a low-cost solution that can be easily integrated with the current optical network devices and infrastructure. Unlike other QKD technologies, a CV protocol requires complex and highly computationally demanding digital signal processing (DSP) operations. In that sense, parallel computation tools such as field programmable gate arrays (FPGAs) represent a key element for the practical implementation of this quantum technology and to scale its performance in terms of distance and secret key rate indicators. This work presents an FPGA-based implementation of the physical layer of a CV-QKD transmitter. The proposed architecture and employed protocols are described, and hardware implementation aspects are discussed, including resource occupation analysis, configuration parameters, and timing issues.
Integrated photonics presents an opportunity for low-cost, lightweight and highly-reproducible quantum cryptographic systems. We show that incorporating integrated photonics within pluggable modules a chip-based QKD system operating in real time and with highly competitive secure key rates can be realised with room temperature single photon detectors. The pluggable modules also benefit from their ability to be easily upgraded and replaced so that as the technology matures the system performance can be further enhanced. We also show that our system can be used with standard classical cryptography systems enabling secure data transfer at 100G.
This paper investigates the problem of integrating quantum-secured communication channels, implemented on the basis of nanophotonic chips, into corporate information systems, taking into account the requirements for scalability, manageability, compatibility with classical telecommunication protocols, and centralized security management.It is noted that the vast majority of current implementations of quantum key distribution (QKD) technologies are focused on the physical data transmission layer and do not provide an adequate level of integration with the software and hardware infrastructure of corporate environments, which significantly limits the possibilities of their practical implementation.An architecture for software-defined quantum-secured communication channels is proposed, based on the concept of functional division of the system into a quantum data transmission layer and a software control layer.Within the developed architecture, key functional components of the control plane are defined, in particular, a quantum key management service, modules for the software orchestration of quantum channels, adaptive routing mechanisms, as well as interfaces for interaction with corporate access management systems, security policies, and classical secure data exchange protocols.
Abstract In the domain of quantum-secure communications, post-processing emerges as a critical mechanism to ensure the security and integrity of the generated keys generated by quantum key distribution (QKD). However, existing post-processing frameworks often lack universality, being highly tailored to single-algorithm implementations and frequently neglecting key aspects such as system scalability and integration. To address these limitations, we present a novel system-on-chip (SoC) architecture for QKD post-processing, built around a co-designed framework featuring a RISC-V soft-core processor. This architecture incorporates core functionalities essential to QKD post-processing, including privacy amplification, information reconciliation, and high-speed communication interfaces. By leveraging the flexibility of the open-source RISC-V instruction set, the system achieves enhanced adaptability and energy efficiency. Additionally, a separated-bus architecture is employed, decoupling data and instruction buses to optimize data transfer efficiency and overall system performance, paving the way for scalable and high-throughput quantum communication systems. The system is deployed on the Xilinx Kintex Ultrascale series development board. At the Bob side, with a frame length of 16 384, the information reconciliation module and the privacy amplification module achieves throughputs of 29.73 Mbps and 131.07 Mbps, respectively.