We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm2process.
We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm2process.
Superconductor digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times gain in speed and more than 100 reduction in power consumption over mainstream CMOS devices. However, the necessity of cooling down to 4 K and modest degree of integration density currently available mean that employing RSFQ is reasonable only for the tasks that are impossible or ineffective to implement in CMOS technology. One of the promising applications of the RSFQ technology is Digital Signal Processing (DSP) for telecommunications. Interference cancellation is a bottleneck for all existing systems in terms of the performance gain that is theoretically possible and technically realizable using conventional technology. The crucial factor is computational complexity required to handle multiple access interference. The general approach is to compute the interference using available data about propagation channels and then either remove it from received signal or use to predistort the transmitted signal. Computation of the interference matrix can easily fall into 100 Gops range, furthermore, the most e±cient algorithms are based on successive iterations. This requires not only high overall performance of the DSP but also high actual clock rate.This thesis reports a proposed architecture of an RSFQ Successive Interference Canceller and a design of an RSFQ Digital Signal Processor based on hybrid RSFQ-CMOS memory suitable for a general matrix on matrix multiplication algorithm. The processor consists of an RSFQ Multiply-Accumulate Unit, memory caches and a synchronization block, partitioned into multiple chips, and a large CMOS memory.The complexity of the RSFQ DSP is 10x10 multiplication, rounding to 14 bits, 18 bits accumulator length and 3.7 Kb memory cache. In order to implement the RSFQ DSP, we have developed approach to simulate and describe the RSFQ circuits using VHDL. The maximum simulated clock frequency is equal to 24 GHz for Hypres 4.5 kA/cm2 process and optimum communication bandwidth with CMOS memory is 2 Gbps.Components of the processor such as 4x4 two's complement and 5x5 parallel multipliers, 4x5, 20x5 and 4x15 parallel shift registers, a 5-bit serial adder have been designed and experimentally tested. The simplified version of the RSFQ DSP consisting of a 4x4 MAC with rounding to 5 bits and 17x6 memory caches has been designed for Hypres 4.5 kA/cm2 process and fabricated.
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.
Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.
This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRWs 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.
We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.>