Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Japanese Journal of Applied Physics

Large-Scale Emulation of Quantum Computing Based on Nonzero State Transitions

Minoru Fujishima, Kento Inai, Tetsuro Kitasho, Koichiro Hoh

Published Apr 1, 2004• 1 citation
Publisher

Abstract

Quantum computing realizes high-speed calculation with massive-parallel computing of quantum state transitions. The quantum computing emulator, however, must be able to manipulate exponentially increasing states as the problem scale increases. To reduce the number of quantum states to be manipulated in the emulator, we have focused on the quantum-state transitions in a quantum computer. In this paper, an emulator representing the state transitions with the location of a nonzero quantum state is proposed. As a result, the emulation of larger-scale quantum algorithms can be realized with a finite amount of hardware.

DOI
10.1143/jjap.43.1690

Related papers

High-speed quantum-computing emulator utilizing a dedicated processor

Minoru Fujishima, Koichiro Hoh

A quantum computer is highly promising and widely studied since it enables a much higher calculation speed than current computers. Due to physical limitations, however, the current quantum computer can only solve much smaller scale problems than conventional computers. In order to process a large-scale problem at high speed, we have been studying a quantum computing emulator utilizing semiconductor memories. As a result, we have realized a dedicated processor that solves search problems, such as the satisfiability problem, at much higher speed than current computers. Consequently, without using "quantum process," the possibility of a quantum computer executing a large-scale problem is shown.

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE•May 9, 2003•2 citations

Parallel Quantum Computing Emulation

Brian R. La Cour, S. Andrew Lanham, Corey I. Ostrove

Quantum computers provide a fundamentally new computing paradigm that promises to revolutionize our ability to solve broad classes of problems. Surprisingly, the basic mathematical structures of gate-based quantum computing, such as unitary operations on a finite-dimensional Hilbert space, are not unique to quantum systems but may be found in certain classical systems as well. Previously, it has been shown that one can represent an arbitrary multi-qubit quantum state in terms of classical analog signals using nested quadrature amplitude modulated signals. Furthermore, using digitally controlled analog electronics one may manipulate these signals to perform quantum gate operations and thereby execute quantum algorithms. The computational capacity of a single signal is, however, limited by the required bandwidth, which scales exponentially with the number of qubits when represented using frequency-based encoding. To overcome this limitation, we introduce a method to extend this approach to multiple parallel signals. Doing so allows a larger quantum state to be emulated with the same gate time required for processing frequency-encoded signals. In the proposed representation, each doubling of the number of signals corresponds to an additional qubit in the spatial domain. Single quit gate operations are similarly extended so as to operate on qubits represented using either frequency-based or spatial encoding schemes. Furthermore, we describe a method to perform gate operations between pairs of qubits represented using frequency or spatial encoding or between frequency-based and spatially encoded qubits. Finally, we describe how this approach may be extended to represent qubits in the time domain as well.

arXiv:1908.06445•IEEE International Conference on Rebooting Computing (ICRC)•Nov 1, 2018•5 citations

Quantum-inspired on-chip parallel processors

Minoru Fujishima

A quantum computer has been the focus of considerable attention since it realizes a much higher operating speed than conventional computers. However, there are many important issues regarding algorithms as well as hardware in the realization of a quantum computer. To realize the calculation speed of a quantum computer, several quantum-computing emulators utilizing parallel operation using integrated circuits were fabricated. Consequently, an emulator of 75 quantum bits was realized, and the feasibility of a high-speed quantum-computing emulator using integrated circuits has been proved.

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE•May 25, 2004•0 citations

FPGA-Based Circuit Model Emulation of Quantum Algorithms

Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani +1 more

It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.

IEEE Computer Society Annual Symposium on VLSI•Jan 1, 2008•43 citations

FPGA-based high-speed emulator of quantum computing

Minoru Fujishima

Quantum computers are believed to perform high-speed calculations, compared with conventional computers. However, the quantum computer has inherent issues. Firstly, it solves NP (non-deterministic polynomial) problems at a high speed only when a periodic function can be used in the process of calculation. Secondly, it is extremely difficult to increase the problem scale to be solved, which is determined by the number of quantum bits. To overcome the restrictions stemming from the quantum algorithm, we are studying the emulation by a FPGA (field programmable gate array). In this paper, first, it is explained why a periodic function is required for the algorithm of a quantum computer. Then, it is shown that the hardware emulator can solve NP problems at a high speed without using a periodic function.

International Conference on Field-Programmable Technology (FPT)•Jun 30, 2004•25 citations

Improving Emulation of Quantum Algorithms using Space-Efficient Hardware Architectures

Naveed Mahmud, Esam El‐Araby

With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.

IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)•Jul 1, 2019•2 citations
Quantum computing realizes high-speed calculation with massive-parallel computing of quantum state transitions. The quantum computing emulator, however, must be able to manipulate exponentially increasing states as the problem scale increases. To reduce the number of quantum states to be manipulated in the emulator, we have focused on the quantum-state transitions in a quantum computer. In this paper, an emulator representing the state transitions with the location of a nonzero quantum state is proposed. As a result, the emulation of larger-scale quantum algorithms can be realized with a finite amount of hardware.
A quantum computer is highly promising and widely studied since it enables a much higher calculation speed than current computers. Due to physical limitations, however, the current quantum computer can only solve much smaller scale problems than conventional computers. In order to process a large-scale problem at high speed, we have been studying a quantum computing emulator utilizing semiconductor memories. As a result, we have realized a dedicated processor that solves search problems, such as the satisfiability problem, at much higher speed than current computers. Consequently, without using "quantum process," the possibility of a quantum computer executing a large-scale problem is shown.
Quantum computers provide a fundamentally new computing paradigm that promises to revolutionize our ability to solve broad classes of problems. Surprisingly, the basic mathematical structures of gate-based quantum computing, such as unitary operations on a finite-dimensional Hilbert space, are not unique to quantum systems but may be found in certain classical systems as well. Previously, it has been shown that one can represent an arbitrary multi-qubit quantum state in terms of classical analog signals using nested quadrature amplitude modulated signals. Furthermore, using digitally controlled analog electronics one may manipulate these signals to perform quantum gate operations and thereby execute quantum algorithms. The computational capacity of a single signal is, however, limited by the required bandwidth, which scales exponentially with the number of qubits when represented using frequency-based encoding. To overcome this limitation, we introduce a method to extend this approach to multiple parallel signals. Doing so allows a larger quantum state to be emulated with the same gate time required for processing frequency-encoded signals. In the proposed representation, each doubling of the number of signals corresponds to an additional qubit in the spatial domain. Single quit gate operations are similarly extended so as to operate on qubits represented using either frequency-based or spatial encoding schemes. Furthermore, we describe a method to perform gate operations between pairs of qubits represented using frequency or spatial encoding or between frequency-based and spatially encoded qubits. Finally, we describe how this approach may be extended to represent qubits in the time domain as well.
A quantum computer has been the focus of considerable attention since it realizes a much higher operating speed than conventional computers. However, there are many important issues regarding algorithms as well as hardware in the realization of a quantum computer. To realize the calculation speed of a quantum computer, several quantum-computing emulators utilizing parallel operation using integrated circuits were fabricated. Consequently, an emulator of 75 quantum bits was realized, and the feasibility of a high-speed quantum-computing emulator using integrated circuits has been proved.
It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.
Quantum computers are believed to perform high-speed calculations, compared with conventional computers. However, the quantum computer has inherent issues. Firstly, it solves NP (non-deterministic polynomial) problems at a high speed only when a periodic function can be used in the process of calculation. Secondly, it is extremely difficult to increase the problem scale to be solved, which is determined by the number of quantum bits. To overcome the restrictions stemming from the quantum algorithm, we are studying the emulation by a FPGA (field programmable gate array). In this paper, first, it is explained why a periodic function is required for the algorithm of a quantum computer. Then, it is shown that the hardware emulator can solve NP problems at a high speed without using a periodic function.
With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.