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International Conference on Computer and Information Technology (ICCIT)

Construction of a multi-level Hierarchical Quasi-Cyclic matrix with layered permutation for partially-parallel LDPC decoders

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz

Published Dec 1, 2010• 5 citations
Publisher

Abstract

Implementation of partially-parallel (Low-Density Parity-Check) LDPC decoders using unstructured random matrices is very complex and requires huge hardware resources. To alleviate the complexity and minimize resource requirements, structured LDPC matrices are used. This paper presents a novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) structured matrix for LDPC decoders. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMAX, WLAN and DVB-S2. In addition, different combinations of permuted sub-matrices are inserted in layers, to provide virtual randomness in the LDPC matrix. Simulations results show that the HQC matrices generated using the proposed technique have a marginal loss of less than 0.1 dB at a bit error rate (BER) performance of 10-5, compared to unstructured random matrices. The proposed matrix therefore provides BER performance close to random matrices while significantly reducing hardware resource requirements.

DOI
10.1109/iccitechn.2010.5723842

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Implementation of partially-parallel (Low-Density Parity-Check) LDPC decoders using unstructured random matrices is very complex and requires huge hardware resources. To alleviate the complexity and minimize resource requirements, structured LDPC matrices are used. This paper presents a novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) structured matrix for LDPC decoders. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMAX, WLAN and DVB-S2. In addition, different combinations of permuted sub-matrices are inserted in layers, to provide virtual randomness in the LDPC matrix. Simulations results show that the HQC matrices generated using the proposed technique have a marginal loss of less than 0.1 dB at a bit error rate (BER) performance of 10-5, compared to unstructured random matrices. The proposed matrix therefore provides BER performance close to random matrices while significantly reducing hardware resource requirements.
A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMax, WLAN and DVB-S2. In addition, different combinations of permuted random sub-matrices are embedded in layers, to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated by using the proposed technique has bit error rate (BER) performance very close to that of unstructured random matrices. A prototype model of partially-parallel decoder architecture has been designed by using the various matrix configurations available in the proposed technique. FPGA design results show that the proposed decoder is resource efficient and the power requirements are comparable to that of ASIC based decoders.
Abstract—Hardware implementation of partially-parallel Low-Density Parity-Check (LDPC) decoders using unstructured random matrices is very complex and requires huge hardware resources. To alleviate the complexity and minimize resource requirements, structured LDPC matrices are used. This paper presents a novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) structured matrix for LDPC decoder. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMAX, WLAN and DVB-S2. In addition, different combinations of permuted sub-matrices are inserted in layers at different levels of matrix hierarchy to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated using the proposed technique have a marginal loss of less than 0.1 dB at a bit error rate (BER) performance 10-5 compared to unstructured random matrices. A hardware model of the proposed matrix structure has been developed and synthesized on Xilinx FPGA to verify the flexibility features, hardware requirements and to analyze the performance of the LDPC decoder. Index Terms—Digital communication, error correction codes, flexible structures, cyclic codes, logic design, field programmable gate array I.
Cyclically-coupled quasi-cyclic low-density parity-check (CC-QC-LDPC) codes are a new class of QC-LDPC codes which can achieve excellent error performance and relatively low hardware requirement. In this paper, we modify the CC-QC-LDPC code construction by using random permutation matrices instead of circulant permutation matrices, forming the “random-permutation-matrix-based CC-LDPC (RP-CC-LDPC) code”. The objective is to achieve a better error performance under the same code length. We simulate the bit error rate using FPGA simulations. We also compare the BER results and decoder complexity of the above codes with those of regular and irregular QC-LDPC codes under the same code length and code rate.
There are many low-density parity-check (LDPC) decoder architectures in the literature most of which are based on structured codes. Besides been specific to a particular class of codes, suggested architectures are limited in scalability. The major challenge in decoder design and implementation is the consideration of several strongly interrelated factors. These factors affect decoder computation and communication complexity, and error-correcting performance. In this paper we present a low-complexity, flexible and scalable LDPC decoder architecture for quasi-cyclic codes that supports multiple code designs (size, weights, rates, regular and irregular). The architecture is a result of a combination of flexible code construction and computation overlapping techniques. The architecture is based on overlapping techniques that allow sequential processing of check and variable nodes. The overlapping techniques lead to a low-complexity decoder interconnect compared to the existing techniques as they allow serial processing of code sub-matrices as compared to parallel processing of all sub-matrices in the existing overlapping technique. Although the architecture is based on quasi-cyclic codes, it can also be applied to random or other structured codes making it the most flexible, scalable and high-throughput partly-parallel LDPC decoder architecture.
The layered scheme is famous for its efficiency and high throughput structure in decoding of LDPC codes, especially the quasi-cyclic LDPC codes, whose parity check matrices are made of cyclically-shifted identity matrices, which can be used as natural partitions of decoding layers. However, for many QC-LDPC codes, it leads to serious routing congestion if the cyclically shifted identity matrix size is taken directly as the layer partition and parallel factor in decoding. In this paper, a parity-check matrix reordering method is introduced, which can lower the decoding parallelism while keeping the layered decoding structure at the same time. The LDPC codes in DVB-S2/T2 standards are taken as an example to illustrate the proposed method, simulation and FPGA implementation shows that the method is effective in reducing the total decoder cost.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.