Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.
Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.
Low-density parity-check (LDPC) codes had a renaissance when they were rediscovered in the 1990’s. Since then LDPC codes have been an important part of the field of error-correcting codes, and have been shown to be able to approach the Shannon capacity, the limit at which we can reliably transmit information over noisy channels. Following this, many modern communications standards have adopted LDPC codes. Error-correction is equally important in protecting data from corruption on a hard-drive as it is in deep-space communications. It is most commonly used for example for reliable wireless transmission of data to mobile devices. For practical purposes, both encoding and decoding need to be of low complexity to achieve high throughput and low power consumption. This thesis provides a literature review of the current state-of-the-art in encoding and decoding of LDPC codes. Message- passing decoders are still capable of achieving the best error-correcting performance, while more recently considered bit-flipping decoders are providing a low-complexity alternative, albeit with some loss in error-correcting performance. An implementation of a low-complexity stochastic bit-flipping decoder is also presented. It is implemented for Graphics Processing Units (GPUs) in a parallel fashion, providing a peak throughput of 1.2 Gb/s, which is significantly higher than previous decoder implementations on GPUs. The error-correcting performance of a range of decoders has also been tested, showing that the stochastic bit-flipping decoder provides relatively good error-correcting performance with low complexity. Finally, a brief comparison of encoding complexities for two code ensembles is also presented.
An improved bit-flipping(BF) algorithm with low complexity for decoding structured low-density parity-check codes(LDPC) is proposed to improve the performance of the hard-decision BF algorithm.The hard-decision bits are divided into two groups based on the magnitudes of the received symbols,and at each iteration,the proposed algorithm can flip more than one bit with using two thresholds,and the flipping error probability is effectively decreased.The improved BF algorithm requires some real number comparisons before iterations and requires only logical operations during the iterations.Compared with the weighted bit-flipping algorithm and its modifications,the new method is with significantly lower complexity.Simulations show that the proposed algorithm is provided with very fast convergence speed and excellent performance with significantly low complexity.
A new class of iterative bit flipping (BF) decoding algorithms adapted for low-density parity check (LDPC) convolutional codes is proposed. Compared with Gallager's original BF algorithm, the new BF algorithms improve both the coding gain and the error correction speed. At a bit error rate (BER) of 10 , the best of the new bit-flipping algorithms achieves, after only 6 iterations and with much simpler decoding hardware, a coding gain within 3.5 dB of that of the conventional min-sum belief propagation decoding algorithm.
The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
Based on decoding performance, complexity and latency of finite-geometry low-density parity-check (LDPC) codes, an efficient decoding algorithm is proposed. The algorithm is a hybrid bit-flipping (BF)/majority-logic (MLG) algorithm. In the algorithm, there are two stages. At the first stage, a code is decoded with bit-flipping (BF) with a small fixed number of iterations. Then the output from bit-flipping (BF) decoder is decoded by majority-logic (MLG) decoding. And in bit-flipping (BF) decoding, a new method is used to find the least reliable position. In the hybrid algorithm, there aren't real operations. Simulation results show that the algorithm provides 0.3dB coding gain over weight bit-flipping (WBF) decoding, and within 1 dB away from sum-product algorithm (SPA) decoding.