Quantum algorithms can be written down in several forms, one of the most common is the quantum circuit representation using discrete gates. The challenge in assessing the computational cost then becomes counting those gates, with realistic costs assigned to each gate. Moreover, interacting pairs of qubits inside most quantum computers will require moving qubits. In many architectures, this will involve cellular automaton-like swapping of qubits. In general, the depth will be described in number of quantum error correction (QEC) cycles, while the total cost will be space-time ``volume'' consisting of the number of qubits involved over that set of QEC cycles. This implies that accurate estimates can be made only in the context of a particular architecture and error correction mechanism.
The existence of algorithm to machine gap has been accepted by the quantum computing domain experts, as the research community is struggling to realize the real power of quantum computing. The prime factor contributing to this gap is the large amount of quantum error correction (QEC) that is required during the execution of a quantum algorithm. For serial quantum computers, with just one processing zone, the coherence time of the qubits would have to grow with the increase in number of qubits, which is not realistic. To this end, the researchers have proposed a "Software-Enabled Vertical Integration and Co-Design", which helps in developing optimized quantum compilers and produce easily verifiable solutions. The other option is to either increase the coherence time, decrease the time per quantum gate operation. However, both of these does not seem to be feasible, because both will lead to increase in execution time, albeit reducing the quantum error rate. Therefore, the feasible solution is to parallelize the quantum information processing (QIP), or the quantum instructions. In this paper, we design a simple quantum instruction set architecture (QISA) and a quantum pipelined architecture (QuPA). The proposed QISA is very similar to the classical instruction set architecture, except that the opcode is initially in an equal superposed state. Also the proposed QISA is grouped based on a certain common prefix, which helps to decode a particular (or group of) operation(s) with a higher probability. We demonstrate how the proposed QISA can be executed over the proposed QuPA with much less quantum cost compared to a general serial architecture. We show that the proposed QuPA has a gate cost of O(2m) compared to the gate cost of the serial architecture, which is O(2n), where m ≤ n.
In recent years, interest in quantum computers has grown significantly. While commercial quantum computers are not available yet, both private and public sector investment into developing quantum computers has developed considerably. One of the key challenges in quantum computing is optimizing the performance of the quantum hardware devices. Different factors can be put into consideration regarding this point, including the number of gates used by the processors to execute different quantum computations and operations. This paper focuses on developing quantum hardware metrics that can be used to measure the performance of a quantum processor in terms of number of quantum gates needed to execute different quantum algorithms. The proposed metrics have been implemented and experimental evaluations have been conducted on various IBM back-end Quantum Computers and using 4 different algorithms: a 5-Qubit entangled circuit algorithm, a 5-Qubit implementation of Grover’s quantum search algorithm, a 5-Qubit implementation of Simon’s quantum algorithm and the 7-Qubit implementation of Steane’s error correction quantum algorithm. In addition, quantitative data on the number of quantum gates used by quantum processors to execute the different quantum algorithms were gathered, which enabled the analysis of how the availability and compatibility of different gate sets affect the overall number of quantum gates needed in the execution of the different quantum algorithms.
The emerging field of quantum resource estimation is aimed at providing estimates of the hardware requirements (`quantum resources') needed to execute a useful, fault-tolerant quantum computation. Given that quantum computers are intended to compete with supercomputers, useful quantum computations are likely to involve the use of millions of qubits and error correction clock cycles. The compilation and benchmarking of these circuits depends on placement and routing algorithms, which are infeasible to construct at scale by hand. We offer a compiler that transforms a quantum circuit into a sequence of lattice surgery operations. The compiler manages memory in terms of surface code patches and costs the space-time volume and cycle counts of the input circuits. These compiled lattice surgery objects are then recursively repurposed as gates for larger scale compilations. Our code is available on GitHub under a permissive software license and we welcome community contributions.
A defining feature of topologically ordered states of matter is the existence of locally indistinguishable states on spaces with nontrivial topology. These degenerate states form a representation of the mapping class group (MCG) of the space, which is generated by braids of defects or anyons, and by Dehn twists along noncontractible cycles. These operations can be viewed as fault-tolerant logical gates in the context of topological quantum error correcting codes and topological quantum computation. Here, we show that braids and Dehn twists can in general be implemented by a constant depth quantum circuit, with a depth that is independent of code distance
d and system size. The circuit consists of a constant depth local quantum circuit (LQC) implementing a local geometry deformation of the quantum state, followed by a permutation on (relabeling of) the qubits. The permutation requires permuting qubits that are separated by a distance of order
d; it can be implemented by collective classical motion of mobile qubits or as a constant depth circuit using long-range SWAP operations (with a range set by
d) on immobile qubits. We further show that (i) applying a given braid or Dehn twist
k times can be achieved with
O(logk) time overhead, independent of code distance and system size, which implies an exponential speedup for certain logical gate sequences by trading space for time, and (ii) an arbitrary element of the MCG can be implemented by a constant depth (independent of
d) LQC followed by a permutation, where in this case the range of interactions of the LQC grows with the number of generators in the presentation of the group element. Applying these results to certain non-Abelian quantum error correcting codes demonstrates how universal logical gate sets can be implemented on encoded qubits using only constant depth unitary circuits.