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An Improvement on the Soft Reliability-Based Iterative Majority-Logic Decoding Algorithm for LDPC Codes

Telex M. N. Ngatched, Attahiru Sule Alfa, Jun Cai

Published Dec 1, 2010• 4 citations
Publisher

Abstract

This paper presents an improvement of the reliability-based iterative majority-logic decoding algorithms for regular low-density parity-check (LDPC) codes proposed by Huang et al. We improve the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration with some kind of reliability measures of the check-sums that are orthogonal on the considered bit. The improved algorithm achieves a significant gain over the standard one with only a modest increase in computational complexity.

DOI
10.1109/glocom.2010.5684111

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IEEE Transactions on Circuits & Systems II Express Briefs•Aug 30, 2019•7 citations
This paper presents an improvement of the reliability-based iterative majority-logic decoding algorithms for regular low-density parity-check (LDPC) codes proposed by Huang et al. We improve the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration with some kind of reliability measures of the check-sums that are orthogonal on the considered bit. The improved algorithm achieves a significant gain over the standard one with only a modest increase in computational complexity.
A reliability-based iterative majority-logic decoding algorithm for regular low-density parity-check (LDPC) codes was recently proposed by Huang et al. In this paper we present an improved version of that algorithm by introducing a different reliability measure for each check-sum of the parity-check matrix, and taking it into account in the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration. Some simulations results are given, which show that the new algorithm, while requiring very little additional computational complexity, not only achieves a considerable error performance gain over the standard one, but also, importantly, outperforms the iterative decoding based on belief propagation (IDBP), especially for short and medium block length finite-geometry (FG) LDPC codes.
Non-binary low-density parity-check (LDPC) codes have some advantages as opposed to their binary counterparts, but unfortunately their decoding complexity is a significant challenge. Hence, the iterative soft-reliability-based (ISRB) majority-logic decoding algorithm is attractive for non-binary LDPC codes, since it involves only finite field additions and multiplications as well as integer additions and comparisons. In this paper, we propose an improved ISRB majority-logic decoding algorithm by using a new reliability update. Our improved algorithm achieves better error performance and faster convergence, while further reducing the computational complexity. For instance, for a (16, 16)-regular (255, 175) cyclic Euclidean geometry LDPC code over GF(28), the proposed algorithm achieves a 0.15 dB coding gain and improves the convergence speed by 10% at a block error rate of 10-4versus the ISRB majority-logic decoding algorithm. Compared with the ISRB majority-logic decoding algorithm, the proposed algorithm requires the same numbers of finite field additions and multiplications but fewer integer additions and comparisons. Furthermore, the ISRB majority-logic decoding algorithm is based on the accumulation of reliability information, and hence the numerical range of the reliability information increases with iterations. In contrast, the proposed reliability update has a fixed numerical range and thus simplifies hardware implementations.
Non-binary low-density parity-check (LDPC) codes have some advantages over their binary counterparts, but unfortunately their decoding complexity is a significant challenge. The iterative hard- and soft-reliability based majority-logic decoding algorithms are attractive for nonbinary LDPC codes, since they involve only finite field additions and multiplications as well as integer operations and, hence, have significantly lower complexity than other algorithms. In this paper, we propose two improvements to the majority-logic decoding algorithms. Instead of the accumulation of reliability information in the existing majority-logic decoding algorithms, our first improvement is a new reliability information update. The new update not only results in better error performance and fewer iterations on average, but also further reduces computational complexity. Since existing majority-logic decoding algorithms tend to have a high error floor for codes whose parity check matrices have low column weights, our second improvement is a reselection scheme, which leads to much lower error floors, at the expense of more finite field operations and integer operations, by identifying periodic points, reselecting intermediate hard decisions, and changing reliability information.
Non-binary low-density parity-check (NB-LDPC) codes tend to exhibit much better performance than their binary counterparts while suffering from very high computational complexity. As a type of hard-decision NB-LDPC decoding algorithm, the iterative reliability-based majority-logic decoding (IRB-MLGD) algorithms are attractive for their low computation complexity, coming with obvious performance degradation. Aiming at improving the error-correction performance, in this paper, we introduce few redundant bits to the original NB-LDPC encoding and the corresponding checksum operations to the improved iterative soft reliability-based (IISRB)-MLGD. Based on the joint coding and decoding method, the obtained redundancy-aided (RA)-IISRB decoding algorithm shows significant performance improvement while maintaining the low-complexity property. Simulation results demonstrate that the proposed algorithm can achieve a more than 1.0dB extra coding gain over the original IISRB with a slight decrease of code rate.
An attenuated iterative reliability-based majority-logic (AIML) decoding algorithm for low-density parity-check (LDPC) codes is proposed. This novel algorithm is devised based on the orthogonal check-sums of the one-step majority-logic decoding algorithm in conjunction with certain of reliability measures of the received symbols. The computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that in binary input-additive white Gaussian noise channel, the AIML algorithm outperforms other popular iterative reliability-based majority-logic decoding algorithms with a slight increase in computational complexity. With maximum iterations five and fifty, the AIML algorithm can achieve almost identical error performance for LDPC codes. No error floor effect can be observed for AIML algorithm down to the bit error rate (BER) of 10−8, while error floor appears for sum product algorithm (SPA) around the BER of 10−7even with maximum iteration 100. The inherent feature of parallel decoding for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping algorithm.
Non-binary low-density parity-check (NB-LDPC) codes usually exhibit much better performance than their binary counterparts. Among NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding (MLGD) algorithms are attractive for their low computation complexity, at the cost of performance degradation. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a clipped-modified (CM)-IISRB algorithm, which achieves better decoding performance with lower computational complexity. First, two modifications are introduced to the IISRB algorithm, which considerably reduces the decoding complexity with negligible performance loss. Second, an unsaturated-clipping method that facilitates significant performance improvement is presented. Simulation results show that the new algorithm outperforms the IISRB by about 0.2dB for the 256-ary (255, 175) example code. Moreover, based on a new storage reduction method, an optimized architecture is developed for the CM-IISRB algorithm. Synthesis results demonstrate that the proposed decoder can achieve very low hardware complexity, comparable to that of the iterative hard reliability-based (IHRB) decoder.