Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IFIP Wireless Days

Decoding architectures for Projective Geometry based LDPC codes

S.G. Harihara, M Girish Chandra, Tarakapraveen Uppalapati, B. S. Adiga

Published Nov 1, 2008• 6 citations
Publisher

Abstract

Projective Geometry (PG) based Low Density Parity Check (LDPC) codes have many useful properties, including easy encoding and decoding by simple majority logic technique. With these useful features, they can be useful error control codes in future. In this paper, we present three novel architectures comprising of one parallel and two semi-parallel decoder architectures for popular PG-based LDPC codes. These architectures have no memory clash and further are reconfigurable for different lengths (and their corresponding rates). The three architectures can be configured either for the regular belief propagation based decoding or majority logic decoding (MLD).

DOI
10.1109/wd.2008.4812880

Related papers

Design and Simulation of Serial and Parallel PG-LDPC Decoder

M. Vijay, K. Mohaneswari

This paper aims to develop a serial and parallel Projective geometric LDPC decoder. The Low-Density Parity-Check codes are among the most powerful forward error correcting codes. LDPC codes are recently used for many high bandwidth applications. A parallel decoding scheme is also proposed to shorten the decoding time. Parallel architecture is employed here to increase the throughput. The proposed decoder is verified through simulation and the results are presented. In this work, Xilinx/Modelsim simulations of the serial and parallel Projective geometric LDPC decoder have been performed With the (7, 3) PG-LDPC code, the implemented parallel decoder requires less decoding time than the serial decoder.

Digital Signal Processing•Jan 1, 2011•0 citations

Low Density Parity Check Codes Based on Finite Geometries: A Rediscovery and More

Yu Kou, Shu Lin, M.P.C. Fossorier

Low density parity check (LDPC) codes with iterative decoding based on belief propagation achieve astonishing error performance close to Shannon limit. No algebraic or geometric method for constructing these codes has been reported and they are largely generated by computer search. As a result, encoding of long LDPC codes is in general very complex. This paper presents two classes of high rate LDPC codes whose constructions are based on finite Euclidean and projective geometries, respectively. These classes of codes a.re cyclic and have good constraint parameters and minimum distances. Cyclic structure adows the use of linear feedback shift registers for encoding. These finite geometry LDPC codes achieve very good error performance with either soft-decision iterative decoding based on belief propagation or Gallager's hard-decision bit flipping algorithm. These codes can be punctured or extended to obtain other good LDPC codes. A generalization of these codes is also presented.

•Oct 20, 1999•89 citations

Parallel reconfigurable decoder architectures for rotation LDPC codes

Zijian Dong, G.-Z. Feng

This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.

IET Communications•Jan 12, 2010•2 citations

Construction of New Finite Geometry Non-Binary LDPC Codes With Reduced Alphabets

Zakaria M’rabet, Fouad Ayoub, Mostafa Belkasmi +1 more

The finite Euclidean and Projective geometry codes are the most known among One-Step Majority-Logic Decodable codes that are Low-Density Parity-Check codes as well. Unfortunately, these codes are rare, and we do not have a great diversity when designing communication systems with a fixed code-length and code rate. Regarding the non-binary Euclidian and projective geometric Codes, each code is restricted to a unique alphabet. To offer a bigger range of possible alphabets for each code, we propose new construction by redefining the incidence vector of the lines of Euclidean and projective geometries over finite fields. This approach leads to an enrichment of the class of EG and PG codes. An error performance study of some new codes has been carried out and shows good results.

International Conference on Advanced Communication Technologies and Networking (CommNet)•Dec 11, 2023•1 citation

Layered Approx-Regular LDPC: Code Construction and Encoder/Decoder Design

Haibin Zhang, Jia Zhu, Huifeng Shi +1 more

Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the Richardson-Urbanke approach: the forward substitution operation is entirely removed and the dense-matrix-vector multiplication is handled using feedback shift-registers. A partially parallel decoder architecture is also designed for LAR-LDPC codes, where a layered modified min-sum decoding algorithm is used to trade off among complexity, speed, and performance. More importantly, the interconnection network, which is inevitable for partially parallel decoders, has much lower hardware complexity compared with that for general LDPC codes. Both the encoder and decoder architectures are highly flexible in code length and code rate.

IEEE Transactions on Circuits and Systems I Regular Papers•Mar 1, 2008•23 citations

Generic Architecture for LDPC Codes Decoding

Frédéric Guilloud

The Low-Density Parity-Check codes are among the most powerful forward error correcting codes, since they enable to get as close as a fraction of a dB from the Shannon limit.This astonishing performance combined with their relatively simple decoding algorithmmake these codes very attractive for the next digital transmission system generations. Itis already the case for the next digital satellite broadcasting standard (DVB-S2), where an irregular LDPC code has been chosen to protect the downlink information. In this thesis, we focused our research on the iterative decoding algorithms and their hardware implementations. We proposed first a suboptimal algorithm named the λ-min algorithm. It reduces significantly the complexity of the decoder without any significant performance loss, as compared to the belief propagation (BP) algorithm. Then we studied and designed a generic architecture of an LDPC decoder, which has been implemented on a FPGA based platform. This hardware decoder enables to accelerate the simulations more than 500 times as compared to software simulations. Moreover, based on an all-tunable design, our decoder features many facilities: It is possible to configure it for a very wide code family, so that the research for good codes is processed faster ; thanks to the genericity of the processing components, it is also possible to optimize the internal coding format, and even to compare various decoding algorithms and various processing schedules. Finally, our experience in the area of LDPC decoders led us to propose a formal framework for analysing the architectures of LDPC decoders. This framework encompassesboth the datapath (parallelism, node processors architectures) and the control mode associated to the several decoding schedules. Thus within this framework, a classification of the different state-of-the-art LDPC decoders is proposed. Moreover, some synthesis of efficient and unpublished architectures have been also proposed.

•Jan 1, 2004•32 citations
Projective Geometry (PG) based Low Density Parity Check (LDPC) codes have many useful properties, including easy encoding and decoding by simple majority logic technique. With these useful features, they can be useful error control codes in future. In this paper, we present three novel architectures comprising of one parallel and two semi-parallel decoder architectures for popular PG-based LDPC codes. These architectures have no memory clash and further are reconfigurable for different lengths (and their corresponding rates). The three architectures can be configured either for the regular belief propagation based decoding or majority logic decoding (MLD).
This paper aims to develop a serial and parallel Projective geometric LDPC decoder. The Low-Density Parity-Check codes are among the most powerful forward error correcting codes. LDPC codes are recently used for many high bandwidth applications. A parallel decoding scheme is also proposed to shorten the decoding time. Parallel architecture is employed here to increase the throughput. The proposed decoder is verified through simulation and the results are presented. In this work, Xilinx/Modelsim simulations of the serial and parallel Projective geometric LDPC decoder have been performed With the (7, 3) PG-LDPC code, the implemented parallel decoder requires less decoding time than the serial decoder.
Low density parity check (LDPC) codes with iterative decoding based on belief propagation achieve astonishing error performance close to Shannon limit. No algebraic or geometric method for constructing these codes has been reported and they are largely generated by computer search. As a result, encoding of long LDPC codes is in general very complex. This paper presents two classes of high rate LDPC codes whose constructions are based on finite Euclidean and projective geometries, respectively. These classes of codes a.re cyclic and have good constraint parameters and minimum distances. Cyclic structure adows the use of linear feedback shift registers for encoding. These finite geometry LDPC codes achieve very good error performance with either soft-decision iterative decoding based on belief propagation or Gallager's hard-decision bit flipping algorithm. These codes can be punctured or extended to obtain other good LDPC codes. A generalization of these codes is also presented.
This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.
The finite Euclidean and Projective geometry codes are the most known among One-Step Majority-Logic Decodable codes that are Low-Density Parity-Check codes as well. Unfortunately, these codes are rare, and we do not have a great diversity when designing communication systems with a fixed code-length and code rate. Regarding the non-binary Euclidian and projective geometric Codes, each code is restricted to a unique alphabet. To offer a bigger range of possible alphabets for each code, we propose new construction by redefining the incidence vector of the lines of Euclidean and projective geometries over finite fields. This approach leads to an enrichment of the class of EG and PG codes. An error performance study of some new codes has been carried out and shows good results.
Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the Richardson-Urbanke approach: the forward substitution operation is entirely removed and the dense-matrix-vector multiplication is handled using feedback shift-registers. A partially parallel decoder architecture is also designed for LAR-LDPC codes, where a layered modified min-sum decoding algorithm is used to trade off among complexity, speed, and performance. More importantly, the interconnection network, which is inevitable for partially parallel decoders, has much lower hardware complexity compared with that for general LDPC codes. Both the encoder and decoder architectures are highly flexible in code length and code rate.
The Low-Density Parity-Check codes are among the most powerful forward error correcting codes, since they enable to get as close as a fraction of a dB from the Shannon limit.This astonishing performance combined with their relatively simple decoding algorithmmake these codes very attractive for the next digital transmission system generations. Itis already the case for the next digital satellite broadcasting standard (DVB-S2), where an irregular LDPC code has been chosen to protect the downlink information. In this thesis, we focused our research on the iterative decoding algorithms and their hardware implementations. We proposed first a suboptimal algorithm named the λ-min algorithm. It reduces significantly the complexity of the decoder without any significant performance loss, as compared to the belief propagation (BP) algorithm. Then we studied and designed a generic architecture of an LDPC decoder, which has been implemented on a FPGA based platform. This hardware decoder enables to accelerate the simulations more than 500 times as compared to software simulations. Moreover, based on an all-tunable design, our decoder features many facilities: It is possible to configure it for a very wide code family, so that the research for good codes is processed faster ; thanks to the genericity of the processing components, it is also possible to optimize the internal coding format, and even to compare various decoding algorithms and various processing schedules. Finally, our experience in the area of LDPC decoders led us to propose a formal framework for analysing the architectures of LDPC decoders. This framework encompassesboth the datapath (parallelism, node processors architectures) and the control mode associated to the several decoding schedules. Thus within this framework, a classification of the different state-of-the-art LDPC decoders is proposed. Moreover, some synthesis of efficient and unpublished architectures have been also proposed.