A superconducting front-end receiver operating in a wide frequency band from 10 to 40 Gb/s could increase the throughput of packet switches. Rapid Single Flux Quantum logic, which has the advantage of high-speed operation at medium integration levels, was used to build receiver components: a multiple bit-rate clock recovery circuit and a demultiplexer. Only 16 heading bits of the packet were required to read the clock frequency in a range from 22.5 to 45 Gb/s. Preliminary experiments showed single bit-rate clock recovery cell operation up to 35 GHz and /spl plusmn/17% bias current margins for a 1:2 demultiplexer. The interface between the receiver and semiconductor components is discussed.
A superconducting front-end receiver operating in a wide frequency band from 10 to 40 Gb/s could increase the throughput of packet switches. Rapid Single Flux Quantum logic, which has the advantage of high-speed operation at medium integration levels, was used to build receiver components: a multiple bit-rate clock recovery circuit and a demultiplexer. Only 16 heading bits of the packet were required to read the clock frequency in a range from 22.5 to 45 Gb/s. Preliminary experiments showed single bit-rate clock recovery cell operation up to 35 GHz and /spl plusmn/17% bias current margins for a 1:2 demultiplexer. The interface between the receiver and semiconductor components is discussed.
Large-scale telecommunication systems in nationwide networks will require routers having a packet switching throughput capacity of over several-tens of Tb/s. In such future high-end routers, packet switches will need higher processing speeds than semiconductor devices can provide. We have demonstrated a 40 GHz clock, 0.8 mW, 160 Gb/s, 4/spl times/4 switch circuit that uses single flux quantum (SFQ) technology. The main components of an SFQ circuit are Josephson junctions and a superconducting loop. In designing the circuit, we have developed two key technologies: an automatic cell placement and route tool to increase designable circuit scale; a passive interconnection to decrease latency. These technologies will enable implementing Tb/s-scale switches and switch schedulers for high-speed packet switching systems.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
We describe the design of a fast single-flux-quantum decoder which can be used, e.g., in fast RAMs, general-purpose microprocessors, and communication channel switches. The core of the circuit is a tree of the single-bit SFQ demultiplexer with toggle (rather than the reset-set) control. Three new RSFQ cells: the demultiplexer, D flip-flop with complementary outputs, and serial XOR with large parameter tolerances (dc bias margins of /spl plusmn/25%, /spl plusmn/26%, and /spl plusmn/27%, respectively) have been developed for the decoder project. We have designed the first 16-bit prototype of the decoder for 1-kA/cm/sup 2/ niobium-trilayer technology and tested it at low frequencies. The circuit was completely operable except for 3 (of 16) output SFQ/DC converters. Simulations show that the circuit should allow data rate in excess of 60 Gbit/s and channel switching time below 20 ps.>
A clock recovery circuit has been successfully tested at frequencies up to 20 GHz. This cell is designed for a rapid-single-flux-quantum (RSFQ) telecommunication data switch. It serves to set the receiver clock in phase with the incoming digital signal. The circuit consists of a dc-to-SFQ converter, ring oscillator [(RO) is a closed-loop RSFQ Josephson transmission line], confluence buffer, and an 8-bit binary counter. The input signal transforms to SFQ pulses, and each pulse resets the phase of the ring oscillator, giving a locking time of 1 bit. Thus, the pull-in (capture) range and hold-in (tracking) range are the same, and strictly depend on the encoding of the input signal. This range is estimated to be about 1 GHz at frequency 20 GHz, if the sequence of consecutive ONEs or ZEROs does not exceed 20 bits. The quality factor QRO of ring oscillator is about 2000, which gives a jitter of 50 fs for a 35-junction RO. A sampling technique was used to demonstrate phase recovery (phase locking) with only one incoming pulse per 512 clock periods.
With regard to sustaining future capacity of network traffic, the current hardware technology has a big bottleneck in terms of power consumption and insufficient operation speed. To overcome this bottleneck, we have developed a single flux quantum (SFQ) packet-switching circuit. We report recent progress in developing the SFQ packet-switching application. First, we demonstrate a 40 GHz, 160 Gb/s, 4 /spl times/ 4 packet switching circuit, which is currently the fastest clock frequency reported packet switch. Then, we describe a currently possible switching module using SFQ technology. Finally, we consider how SFQ technology can be used to scale the packet-switching capacity up to 100 Tbps.
We have designed a speedup buffer (SB) that is indispensable for realizing a high-throughput network switch based on single-flux-quantum (SFQ) technology. The SB performs the rate conversion from 10 to 40 Gbps for the packet data streams fed into the Banyan switch. This approach can reduce the packet-blocking rate, resulting in an increased throughput for the network switch. The SB is composed of a 1:3 stream demultiplexer (SDMUX), three variable-bit-length shift registers (VLSRs) and a 3:1 stream multiplexer, coupled with a controller. We have successfully demonstrated the 1:3 SDMUX and the VLSR. As for the VLSR, we confirmed high-speed operation up to 55 GHz. We have also designed the SB using these components. The SB is a large-scale circuit composed of 11 663 Josephson junctions on a 3.8 × 3.8 mm 2 area. So far, partial operations have been demonstrated experimentally.