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AEU - International Journal of Electronics and Communications

Quasi-cyclic LDPC codes using overlapping matrices and their layered decoders

Beomkyu Shin, Hosung Park, Seokbeom Hong, Jong‐Seon No, Sang‐Hyo Kim

Published Nov 12, 2013• 5 citations
Publisher
DOI
10.1016/j.aeue.2013.10.004

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In low-density parity-check (LDPC) code decoding with the iterative sum-product algorithm (SPA), due to the randomness of the parity-check matrix, H, the overlapping of the check node processing unit (CNU) and variable node processing unit (VNU) in the same clock cycle is difficult. The paper demonstrates that overlapped decoding can be exploited as long as the LDPC matrix is composed of identity matrices and their cyclic-shifted matrices, i.e., the parity-check matrix, H, belongs to a class of quasi-cyclic LDPC codes. It is shown that the number of clock cycles required for decoding can be reduced by 50% when overlapped decoding is applied to a (3,6)-regular LDPC code decoder.
Most communication systems including Wibro use quasi-cyclic LDPC codes composed of circulants. However, it is very difficult to design quasi-cyclic(QC) LDPC codes with optimal degree distribution satisfying conditions on layered decoding and girth due to the restriction of the size of its base matrix. In this paper, we propose a good solution by introducing superposition matrices to QC LDPC codes. We derive the conditions on checking girth of QC LDPC codes with superposition matrices, and propose new decoder to support layered decoding both for original QC LDPC codes and their modifications with superposition matrices. Simulation results show considerable improvements to convergence speed and error-correcting performance of proposed scheme which adopts QC LDPC codes with superposition matrices.
The layered scheme is famous for its efficiency and high throughput structure in decoding of LDPC codes, especially the quasi-cyclic LDPC codes, whose parity check matrices are made of cyclically-shifted identity matrices, which can be used as natural partitions of decoding layers. However, for many QC-LDPC codes, it leads to serious routing congestion if the cyclically shifted identity matrix size is taken directly as the layer partition and parallel factor in decoding. In this paper, a parity-check matrix reordering method is introduced, which can lower the decoding parallelism while keeping the layered decoding structure at the same time. The LDPC codes in DVB-S2/T2 standards are taken as an example to illustrate the proposed method, simulation and FPGA implementation shows that the method is effective in reducing the total decoder cost.