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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

A single-flux-quantum logic prototype microprocessor

Masamitsu Tanaka, Fumiya Matsuzaki, Takaharu Kondo, Nobuo Nakajima, Yuki Yamanashi, Akira Fujimaki, Hisao Hayakawa, Nobuyuki Yoshikawa, Hirotaka Terai, Shinichi Yorozu

Published Sep 28, 2004• 59 citations
Publisher

Abstract

The complete operation of a microprocessor prototype based on the single-flux-quantum (SFQ) logic is described. The 8b SFQ microprocessor, fabricated using niobium Josephson-junction technology, performs computation at a 15.2GHz clock rate with power consumption of 1.6mW. The /spl mu/P contains 5000 Josephson junctions and 1300 cells on a 5mm/sup 2/ IC.

DOI
10.1109/isscc.2004.1332714

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The complete operation of a microprocessor prototype based on the single-flux-quantum (SFQ) logic is described. The 8b SFQ microprocessor, fabricated using niobium Josephson-junction technology, performs computation at a 15.2GHz clock rate with power consumption of 1.6mW. The /spl mu/P contains 5000 Josephson junctions and 1300 cells on a 5mm/sup 2/ IC.
The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low-temperature 4 kA/cm 2 , 1.75-μm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in 2001 are currently under testing at TRW.
A superconductor single-flux-quantum (SFQ) logic 8-bit microprocessor is demonstrated up to 57.2 GHz with a measured power consumption of 11.2 mW. The microprocessor has an ultradeep, gate-level pipelining containing many feedback paths and communications between components. The arrival clock timings at all the logic gates are ultra-precisely tuned using two different clocking schemes, called “concurrent-flow” and “counter-flow,” to achieve extremely high clock frequency operation over 50 GHz. Low-temperature circumstances enable us to conduct super delay-intensive layout design by controlling delays of all waveguide interconnects in the order of sub-picosecond precision.
The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low- temperature 4 kA/cm', 1.75-pm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an %bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-I chips fabricated in 2001 are currently under testing at TRW.
The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.
We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.
Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90?65?nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100?kA?cm?2 to achieve junction speeds approximately 1000?GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250?M Josephson junctions cm?2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200?GHz and place approximately 20?K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip.