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International Journal of Computer Applications

Quantum Cost Realization of Reversible Barrel Shifter

Sagarkumar Buyya, Chaya J. Bhavi

Published Dec 18, 2012• 1 citation
Publisher

Abstract

This paper presents an efficient design of a reversible barrel shifter.It has also been shown that the new circuit outperforms the previously proposed one in terms of number of gates, number of garbage outputs, delay and quantum cost.
DOI
10.5120/9615-4250

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Multiple-valued reversible logic is emerging as a promising computing paradigm as it helps in reducing the width of the reversible or quantum circuits. Further, a barrel shifter that can shift and rotate multiple bits in a single cycle forms the essence of many computing systems. In this paper, we propose an efficient architecture and design of a reversible ternary barrel shifter. The ternary barrel shifter is realized using the Modified Fredkin gates (MFG) and the ternary Feynman gates. The design is evaluated in terms of quantum cost, the number of garbage outputs and the number of ancilla bits. To our knowledge, the use of multiple valued reversible logic for the design of a barrel shifter is being attempted for the first time in the literature.
Reversible logic attains the dominance in the realm of overwhelming research in logic synthesis and also has the significance in the context of quantum computing because of loss-less information processing. Due to low power dissipation, researchers are first designing smaller components with reversible gates, that eventually lead to design reversible computer. In this paper, we propose a robust architecture of logarithmic barrel shifter that performs bidirectional arithmetic and logical shifting, including rotate operation. Incorporating fault tolerance capability, the circuit is designed very efficiently that exhibits superior performance over state-of-the-art design methods in terms of minimum number of gates, garbage outputs, ancilla inputs, quantum cost, delay and others cost factors.
A barrel shifter is a common component in the high-speed processor.It can shift a data word by specified number of bits in one clock cycle.Based on the quantum reversible logic circuit,the shifter with n inputs and m control bits named as a(n,m) shifter.For synthesizing the reversible shifter,the novel method based on the decomposition of the permutation group,it only use(3,1) shifters and controlled swap gates to quickly synthesize any controlled shifter with small quantum cost,and any(n,k) barrel shifter can be obtained by cascading minimal k corresponding(n,1) shifters.
Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of quantum computer and reversible logic, design and implementation of all devices in this logic has received more attention. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated.
In this paper, we propose two new designs for the barrel shifter: i) a quantum ternary unidirectional barrel shifter (Design I) and ii) a quantum ternary bidirectional barrel shifter (Design II). We present the design of Ternary Peres Gate (TPG). The designs of ternary barrel shifters show that circuits are composed of proposed Ternary Peres Gates, Modified Fredkin Gates and Ternary Feynman Gates. A new technique to calculate the ternary quantum gate calculation complexity of ternary circuits has been proposed in the paper. Our circuits perform better than the existing ones in terms of quantum gates, garbage outputs and ternary quantum gate calculation complexity.