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A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders

Ruwan Ratnayake, Erich F. Haratsch, Gu-Yeon Wei

Published Nov 1, 2007• 1 citation
Publisher

Abstract

A bit-node centric decoder architecture for low- density parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less memory compared to other known serial architectures. The hardware requirements are reduced even further for the concatenated detector-decoder system.

DOI
10.1109/glocom.2007.57

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A bit-node centric decoder architecture for low- density parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less memory compared to other known serial architectures. The hardware requirements are reduced even further for the concatenated detector-decoder system.
In this paper, the partial-min algorithms are proposed for updating the check node messages in decoding low-density parity-check (LDPC) codes. The proposed methods can achieve a good performance-versus-complexity tradeoff by reducing both the check node processor complexity and the decoder memory requirements. Float-point and fixed-point simulation results show that a near optimum performance can be maintained. The architecture of a check node processor implementing the partial-min algorithms is also presented. The hardware expense especially the memory requirement is analyzed and compared with normal decoding architectures
In this paper, we introduce a computationally efficient selective node update algorithm for the decoding of low-density parity check codes. Unlike the standard sum-product algorithm, where all bit and check nodes are updated at each decoding iteration, the developed algorithm only updates unreliable check and bit nodes. A simple reliability criteria is developed to determine the active bit and check nodes per decoding iteration. Based on the developed technique, significant computation reductions are achieved with very little or no loss in the BER performance of the LDPC codes. At a WER of 10-5, 91.8% and 72.7% check node and 80% and 41% bit node computation reductions are obtained for a (96, 48) and a (504, 252) LDPC code, respectively. The proposed method can be implemented with a slight modification to the standard sum-product decoding algorithm with negligible additional hardware complexity. From a hardware point of view, the proposed algorithm offers power reductions proportional to the computation savings and it leads to higher decoding speeds in serial implementations by decreasing the number of required memory accesses
This chapter reviews nonbinary low–density parity–check (NB–LDPC) decoder architectures, with emphasis given to algorithmic and architectural modification techniques for the check node units. The belief propagation (BP) for binary low-density parity-check decoding can be extended to decode NB–LDPC codes. In non–binary BP, the check node processing also computes sums of products of probabilities. The computations in non–binary check node processing can be considered as convolutions of the incoming messages. Multiplications in probability domain are implemented as additions in log domain. The most prominent ones are the extended Minsum algorithm and the Min–max algorithm. Both of them are log-domain algorithms. The approximations lead to slight performance loss compared to the BP, the hardware complexity has been greatly reduced in these algorithms, and only additions on the reliability messages are involved in their check node processing. The number of multiplications in the check node processing is reduced in the frequency–domain approach.
We present a memory efficient serial low density parity check (LDPC) decoder that implements a modified sum product algorithm (SPA). The modification is similar to the approximate min constraint presented by C. Jones et al. (see IEEE Conf. Military Commun., MILCOM 2003, p.157-162, 2003) but differs in hardware implementation to suit a serial architecture. Our main contribution is the proposed architecture that exploits the min constraint to reduce the storage of extrinsic messages which forms the bulk of the hardware. The least reliable bit to check input along with the check sum are the only quantities stored in the decoder. Extrinsic message memory reduction increases with the rate of the code and up to 68% saving is achieved for a rate 9/10 code. Simulation results show that the proposed changes do not degrade the bit error rate performance.
Non-binary low-density parity-check (NB-LDPC) codes can achieve higher coding gain than binary LDPC codes when the code length is moderate at the cost of higher complexity. One major step of NB-LDPC decoding is check node processing. Previously, iterative forward-backward approaches are employed to implement this step. However, the storage of the intermediate results of the forward and backward computations requires large memory. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the extended Min-sum NB-LDPC decoding. The proposed scheme only stores a limited number of sorted variable-to-check messages. Then the check-to-variable messages for different variable node are generated independently. For a (837, 726) NB-LDPC code over GF(25), the proposed architecture only requires 64% of the area of the previous design with the same throughput and error-correcting performance.