This chapter reviews nonbinary low–density parity–check (NB–LDPC) decoder architectures, with emphasis given to algorithmic and architectural modification techniques for the check node units. The belief propagation (BP) for binary low-density parity-check decoding can be extended to decode NB–LDPC codes. In non–binary BP, the check node processing also computes sums of products of probabilities. The computations in non–binary check node processing can be considered as convolutions of the incoming messages. Multiplications in probability domain are implemented as additions in log domain. The most prominent ones are the extended Minsum algorithm and the Min–max algorithm. Both of them are log-domain algorithms. The approximations lead to slight performance loss compared to the BP, the hardware complexity has been greatly reduced in these algorithms, and only additions on the reliability messages are involved in their check node processing. The number of multiplications in the check node processing is reduced in the frequency–domain approach.
This chapter reviews nonbinary low–density parity–check (NB–LDPC) decoder architectures, with emphasis given to algorithmic and architectural modification techniques for the check node units. The belief propagation (BP) for binary low-density parity-check decoding can be extended to decode NB–LDPC codes. In non–binary BP, the check node processing also computes sums of products of probabilities. The computations in non–binary check node processing can be considered as convolutions of the incoming messages. Multiplications in probability domain are implemented as additions in log domain. The most prominent ones are the extended Minsum algorithm and the Min–max algorithm. Both of them are log-domain algorithms. The approximations lead to slight performance loss compared to the BP, the hardware complexity has been greatly reduced in these algorithms, and only additions on the reliability messages are involved in their check node processing. The number of multiplications in the check node processing is reduced in the frequency–domain approach.
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance.Although various kinds of low-complexity iterative decoding algorithms have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high complexity and long latency.In this brief, highly efficient check node processing scheme, which the processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are proposed.Compare with previous works, less than 52% could be reduced for the latency of check node unit.In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NB-QC-LDPC decoder.
Compared to binary low-density parity-check (LDPC) codes, nonbinary (NB) LDPC codes can achieve higher coding gain when the codeword length is moderate, but at the cost of higher decoding complexity. One major bottleneck of NB-LDPC decoding is the complicated check node processing. In this paper, a novel relaxed check node processing scheme is proposed for the min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p) can be uniquely represented by a linear combination of p independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then, the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and the overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25) can achieve 52% higher efficiency in terms of throughput-over-area ratio.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding algorithm. The proposed scheme first sorts out a limited number of the most reliable variable-to-check (v-to-c) messages, then the check-to-variable (c-to-v) messages to all connected variable nodes are derived independently from the sorted messages without noticeable performance loss. Compared to the previous iterative forward-backward check node processing, the proposed scheme not only significantly reduced the computation complexity, but eliminated the memory required for storing the intermediate messages generated from the forward and backward processes. Inspired by this novel c-to-v message computation method, we propose to store the most reliable v-to-c messages as “compressed” c-to-v messages. The c-to-v messages will be recovered from the compressed format when needed. Accordingly, the memory requirement of the overall decoder can be substantially reduced. Compared to the previous Min-max decoder architecture, the proposed design for a (837, 726) code overGF(25) can achieve the same throughput with only 46% of the area.
Decoding Algorithms for Nonbinary LDPC Codes Over GF(q)
In this letter, we address the problem of decoding nonbinary low-density parity-check (LDPC) codes over finite fields GF(q), with reasonable complexity and good performance. In the first part of the letter, we recall the original belief propagation (BP) decoding algorithm and its Fourier domain implementation. We show that the use of tensor notations for the messages is very convenient for the algorithm description and understanding. In the second part of the letter, we introduce a simplified decoder which is inspired by the min-sum decoder for binary LDPC codes. We called this decoder extended min-sum (EMS). We show that it is possible to greatly reduce the computational complexity of the check-node processing by computing approximate reliability measures with a limited number of values in a message. By choosing appropriate correction factors or offsets, we show that the EMS decoder performance is quite good, and in some cases better than the regular BP decoder. The optimal values of the factor and offset correction are obtained asymptotically with simulated density evolution. Our simulations on ultra-sparse codes over very-high-order fields show that nonbinary LDPC codes are promising for applications which require low frame-error rates for small or moderate codeword lengths. The EMS decoder is a good candidate for practical hardware implementations of such codes
This paper presents a low-computational algorithm for the check node processing of non-binary low-density parity-check (NB-LPDC) decoders, the base algorithm that we use is the extended min-sum (EMS) algorithm, which has been widely studied in the recent literature, and has been shown to approach the performance of the belief propagation algorithm, with limited complexity. This algorithm, named novel bubble check, can reduce greatly the number of bubbles to be compared, this significant computational reduction is achieved without any performance loss. This algorithm is particularly suitable for NB-LPDC decoders in super-high order fields, which have superior performance in the presence of burst errors.
Non-binary low-density parity-check (NB-LDPC) codes can achieve higher coding gain than binary LDPC codes when the code length is moderate at the cost of higher complexity. One major step of NB-LDPC decoding is check node processing. Previously, iterative forward-backward approaches are employed to implement this step. However, the storage of the intermediate results of the forward and backward computations requires large memory. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the extended Min-sum NB-LDPC decoding. The proposed scheme only stores a limited number of sorted variable-to-check messages. Then the check-to-variable messages for different variable node are generated independently. For a (837, 726) NB-LDPC code over GF(25), the proposed architecture only requires 64% of the area of the previous design with the same throughput and error-correcting performance.