Low Complexity Implementation Of LDPC Decoder using MIN-Sum Algorithm

Geo Niju Shanth, S. Chamandi Priya

Published Jul 12, 2013• 0 citations

Abstract

This paper presents a resource efficient LDPC decoder architecture. The algorithm used for decoding LDPC is the min-sum algorithm. The decoder reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. The algorithm is simulated and the results show that the performance is better than that of other algorithms. This algorithm can be incorporated into partially parallel hardware architecture to get significant savings in hardware resources when implemented in FPGA.

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