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Electronics Letters

Turn-on delay for Josephson logic devices with high damping

Ph. Migny, Bernard Plaçais

Published Sep 2, 1982• 5 citations
Publisher

Abstract

Josephson logic devices exhibit, before switching from superconducting to voltage state, a turn-on delay which depends on current overdrive and damping coefficient. A novel expression describing turn-on delay for heavily damped circuits is proposed. A comparison with numerical calculation is made. As an example of application for this expression, the turn-on delay appearing in the simulation of a damped logic gate switching is discussed.

DOI
10.1049/el:19820525

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afips•Dec 30, 1899•0 citations
Josephson logic devices exhibit, before switching from superconducting to voltage state, a turn-on delay which depends on current overdrive and damping coefficient. A novel expression describing turn-on delay for heavily damped circuits is proposed. A comparison with numerical calculation is made. As an example of application for this expression, the turn-on delay appearing in the simulation of a damped logic gate switching is discussed.
It has generally been assumed that the switching dynamics of Josephson logic devices can be well approximated by treating the Josephson device as a capacitatively-shunted switch which opens instantaneously when a control current crosses threshold. In this approximation, the switching delay is proportional to RC, where R = load resistance and C = device capacitance. However, we show here that the above approximation is quite incorrect in the technologically important case of logic interferometers in which resonances are suppressed by internal damping. We treat in detail the case of damped two-junction interferometers with step-function control current. Analysis of the equations of motion shows that in addition to the RC delay there is an initial turn-on delay during which the output voltage is very small, and which is most pronounced for heavy internal damping. It consists of the time required for the difference in phase between the two junctions to increase to a critical value, followed by approximately the first half-cycle of growth of the average of the junction phases. The turn-on delay is a strong function of overdrive, (i.e., the factor by which the control current amplitude exceeds threshold), being smallest at large overdrives, and scales as (C/i0)1/2, where i0= junction critical current. Hence it can be reduced by miniaturization and/or increased junction current density. For parameter values typical of 5μm Josephson circuit technology, the turn-on delay is on the order of 10pS at large overdrives (≃2).
The time resolution of a Josephson junction sampler depends on the switching time of the junction. This switching time depends on the junctions' plasma frequency and McCumber parameter, but also on the amount of overdrive current applied. An approximate closed form expression is derived for the switching time as a function of the overdrive, excluding damping or noise. A key result is that the switching time depends logarithmically on the overdrive. Numeric simulations are used to justify the approximations made and reveal the dependence on damping. Comparisons are made between the analytic expression and a numeric simulation of the switching time. Application of the results to a Josephson sampler is presented.
For a given level of overdrive, there exists a minimum-width control-current pulse that must be applied to switch a Josephson logic gate. Determination of this minimum pulsewidth is useful in setting limits on the speed of various Josephson circuit configurations and also in finding the narrowest pulse that a Josephson-junction gate can detect when it is employed as a pulse detector. The minimum control-current pulsewidth is a strong function of the overdrive factor of the control current. It scales as(C/I_{m})^{1/2}, where Imis the junction critical current, andCis the capacitance, and is on the order of 10 ps for Josephson quantum interferometers in 5-µm technology. Computer simulations have been done to find the dependence of minimum control-current pulsewidths on overdrive magnitude for a single-junction gate and for two- and three-junction interferometers. Analytic expressions of the minimum control-current pulsewidth that are in good agreement with simulations have been obtained for these three types of Josephson logic gates.
We have simulated fluxon propagation within a Josephson transmission line that is one of the elements of a rapid single flux quantum (RSFQ) circuit. This line is a parallel connection of damped Josephson junctions coupled by superconducting inductances. Geometries with and without mutual inductances between neighboring cells are considered. If the time interval between two fluxons is less than 0.3 φ0Vc−1 (Vc characteristic voltage) a repulsion between them was observed. The repulsion sets a specific time delay between the fluxons that impose a rigid limitation for high frequency performance of RSFQ logic. The delay depends on the shunting parameter, bias current, and values of interconnecting inductances.
Experimental superconducting Josephson devices being investigated for use in digital logic and memory circuits have been demonstrated to switch in the 10 to 100 picosecond (1 picosecond = 10-12 sec) range. Projections based on the operation of individual logic circuits indicate that they may surpass semiconductor circuits in very high performance CPU's. This potential is based on the fact that these circuits dissipate extremely little energy, on the order of 10 to 1000 attojoules (attojoule = 10-18 joule), while operating with subnanosecond delays. It should, therefore, be possible to package Josephson devices very densely and interconnect them by properly terminated superconducting transmission lines so that the fast switching speed of individual circuits is retained throughout large logic networks.
Experimental superconducting Josephson devices being investigated for use in digital logic and memory circuits have been demonstrated to switch in the 10 to 100 picosecond (1 picosecond = 10-12 sec) range. Projections based on the operation of individual logic circuits indicate that they may surpass semiconductor circuits in very high performance CPU's. This potential is based on the fact that these circuits dissipate extremely little energy, on the order of 10 to 1000 attojoules (attojoule = 10-18 joule), while operating with subnanosecond delays. It should, therefore, be possible to package Josephson devices very densely and interconnect them by properly terminated superconducting transmission lines so that the fast switching speed of individual circuits is retained throughout large logic networks.