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IEEE Journal of Solid-State Circuits

Circuit models and applications of the superconducting field-effect transistor

Lance A. Glasser

Published Oct 1, 1989• 16 citations
Publisher

Abstract

Static and dynamic models for the superconducting transistor are developed. The models capture the symmetry of the source-drain structure, incorporate the gate reaction, span the long- and short-channel regimes without discontinuity, and are suitable for circuit simulation. The sensitivity of the drain-to-source critical current to changes in gate charge is shown to control much of the device dynamics. The model is used to investigate several circuit configurations including amplifiers, inverters, latches, flux transfer devices, and phase-locked components.>

DOI
10.1109/jssc.1989.572631

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Static and dynamic models for the superconducting transistor are developed. The models capture the symmetry of the source-drain structure, incorporate the gate reaction, span the long- and short-channel regimes without discontinuity, and are suitable for circuit simulation. The sensitivity of the drain-to-source critical current to changes in gate charge is shown to control much of the device dynamics. The model is used to investigate several circuit configurations including amplifiers, inverters, latches, flux transfer devices, and phase-locked components.>
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We report experimental and theoretical results on the current gain in superconductor-ferromagnetic transistors (SFTs) with the SISFIFS structure [where S, I, and F denote a superconductor (Nb), an insulator (AlOx), and a ferromagnetic material (Ni), respectively]. The Josephson critical current density jcaof the acceptor (SISF) junction in the devices is above 9 kA/cm2, which is higher than that in our previous devices. The critical current gain is defined as |δIca|/|δIi|, where a change |δIi| in the injector (SFIFS junction) current produces a change |δIca| in the acceptor maximum Josephson current. We observed a small-signal gain as high as 7.8 and a large-signal current gain of about 2.2. In addition, we found that the Josephson current of the acceptor junction is sensitive to the state of the ferromagnetic layers. A theoretical model is proposed to describe the nonequilibrium processes in the SFT devices, which agrees with the experimental observations. The calculation shows that, in the present device configuration, the dominant contribution to the gap suppression in the middle Nb electrode is due to the quasiparticle injection; spin injection plays a secondary role. We demonstrate that proper device engineering allows one to efficiently control the maximum Josephson current in the SISF acceptor junction using the quasiparticle injection. We conclude that SFT devices can be used as input/output isolators and amplifiers for memory, digital, and RF applications.
The growing demand for ultra low power computing and the emergence of quantum technologies have intensified interest in cryogenic electronics, particularly superconducting devices. Despite their promise, current controlled superconducting components face fundamental challenges in cascadability, limiting their effectiveness in complex logic architectures. To overcome this, recent efforts have focused on developing gate tunable superconducting devices, such as Josephson junction field effect transistors (JJFETs). However, achieving robust control and sufficient supercurrent gain, both critical for transistor-like performance in logic circuits remains a key challenge. A recent advancement in JJFET design, based on InAs and GaSb heterostructures, demonstrates enhanced gain and favorable device characteristics suitable for circuit integration. Building on this innovation, we propose and analyze fundamental voltage controlled logic topologies using the quantum enhanced JJFET. We develop a Verilog A based circuit compatible compact model of the quantum enhanced JJFET which accurately captures the experimentally observed device characteristics. To ensure cascadability, our logic circuits incorporate the multilayered Heater Nanocryotron (nTron), a superconducting nanowire-based thermal switch. Through simulation based analysis, we demonstrate the successful implementation of fundamental logic gates, including NOT, NAND, and NOR. Furthermore, we design a 3 input majority gate, which plays a pivotal role in quantum and reversible computing due to its universality. Finally, to demonstrate the cascadability of our proposed logic topology, we demonstrate the operation of a 2 input XOR gate based on our designed JJFET based NOT, NAND, and NOR gate.