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IEEE Computer Society Annual Symposium on VLSI

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders

Chetan Kumar Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, V. Sreehari, N. Moorthy Muthukrishnan, Mandalika B. Srinivas

Published Aug 1, 2012• 6 citations
Publisher

Abstract

Reversible computing has emerged as promising technology having its applications in quantum computing, nanotechnology and optical computing. This paper presents design and analysis of reversible ripple, prefix and prefix ripple hybrid adders. Firstly an analysis and comparison of all the existing reversible ripple carry adders is presented. The reversible ripple carry adders are characterized by high quantum depth, low quantum cost and/or low garbage outputs and ancilla inputs bits. Secondly design methodology for reversible prefix adders is presented. The reversible prefix adders are characterized by low quantum depth, high quantum cost and/or high garbage outputs and ancilla inputs bits. Finally design of the proposed reversible prefix-ripple hybrid adders is presented and comparison of the different parameters of reversible ripple, prefix and prefix-ripple hybrid adders is illustrated.

DOI
10.1109/isvlsi.2012.50

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Reversible computing has emerged as promising technology having its applications in quantum computing, nanotechnology and optical computing. This paper presents design and analysis of reversible ripple, prefix and prefix ripple hybrid adders. Firstly an analysis and comparison of all the existing reversible ripple carry adders is presented. The reversible ripple carry adders are characterized by high quantum depth, low quantum cost and/or low garbage outputs and ancilla inputs bits. Secondly design methodology for reversible prefix adders is presented. The reversible prefix adders are characterized by low quantum depth, high quantum cost and/or high garbage outputs and ancilla inputs bits. Finally design of the proposed reversible prefix-ripple hybrid adders is presented and comparison of the different parameters of reversible ripple, prefix and prefix-ripple hybrid adders is illustrated.
Reversible logic is one of the emerging technologies having promising applications in quantum computing. In this work, we present new design of the reversible BCD adder that has been primarily optimized for the number of ancilla input bits and the number of garbage outputs. The number of ancilla input bits and the garbage outputs is primarily considered as an optimization criteria as it is extremely difficult to realize a quantum computer with many qubits. As the optimization of ancilla input bits and the garbage outputs may degrade the design in terms of the quantum cost and the delay, thus the quantum cost and the delay parameters are also considered for optimization with primary focus towards the optimization of the number of ancilla input bits and the garbage outputs. Firstly, we propose a new design of the reversible ripple carry adder having the input carry Co and is designed with no ancilla input bits. The proposed reversible ripple carry adder design with no ancilla input bits has less quantum cost and the logic depth (delay) compared to its existing counterparts. The existing reversible Peres gate and a new reversible gate called the TR gate is efficiently utilized to improve the quantum cost and the delay of the reversible ripple carry adder. The improved quantum design of the TR gate is also illustrated. Finally, the reversible design of the BCD adder is presented which is based on a 4 bit reversible binary adder to add the BCD number, and finally the conversion of the binary result to the BCD format using a reversible binary to BCD converter.
Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry c 0 and no ancilla input bits, and (ii) one with input carry c 0 and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing.
Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs; and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
Reversible logic has represented itself as a prominent technology which plays an important role in Quantum Computing. Theoretically Quantum Computers operates at high speed and consumes less power. Furthermore, Reversible logic can break the conventional speed of power trade-off. To prove this we are implementing Ripple Carry Adder and Carry Look Ahead Adder using reversible logic gates. The paper presents efficient adder circuits using Peres gate, New fault Tolerant gate and Double Feyman gate. The complexity, simulated outputs and the speed parameters for the adder circuit have been indicated using the Quartus II 9.1 edition and Modelsim tool. Moreover, the quantum algorithms can potentially solve NP-complete problems. Furthermore, doing high performance functions beyond the limit of deterministic computer systems is possible by only reversible logic. Quantum operations are unitary in nature which is reversible and hence the arithmetic operations like adders can be implemented using the reversible logic. Likewise, optimized block size, minimum ancillary bits, and one to one mappings of inputs and outputs are obtained in the reversible adder circuit, giving fan out as 1. Hence, the Ripple Carry Adder and Carry look Ahead Adder is providing complexity reduction and high speed, proving to be an efficient and important part in the development of arithmetic blocks of Quantum Computers.
Reversible logic is one of the emerging computational methodologies which assures zero power dissipation through theoretical laws of thermodynamics. It has received significant interest in application on quantum computing, nanotechnologies and low power computing devices. In this work, we present a reversible logic implementation for Binary Coded Decimal (BCD) adder which is designed to obtain lowest quantum cost value. Other parameters such as ancilla input, garbage output and delay are kept at minimal. Experiment result shows that the proposed work outperforms other designs in terms of quantum cost. Considering for a 1 digit BCD adder, it has a 4% improvement in terms of quantum cost compared to the current best existing ones. The improvement range increases as the BCD digit becomes larger.