This paper presents the design of a novel modified Wallace tree multiplier, using the reversible TSG gate proposed by the authors earlier. The novelty of the TSG gate is that it can also work singly as a reversible full adder. The TSG gate is also used in this paper to design various other reversible arithmetic and logical components that can be assembled to realize a primitive reversible/quantum ALU. It is also shown that these components are optimal, in terms of number of reversible gates and garbage outputs, compared to other designs existing in literature.
This paper presents the design of a novel modified Wallace tree multiplier, using the reversible TSG gate proposed by the authors earlier. The novelty of the TSG gate is that it can also work singly as a reversible full adder. The TSG gate is also used in this paper to design various other reversible arithmetic and logical components that can be assembled to realize a primitive reversible/quantum ALU. It is also shown that these components are optimal, in terms of number of reversible gates and garbage outputs, compared to other designs existing in literature.
Reversible logic is now employed in low-power CMOS circuits, optical data processing, DNA calculations, biological studies, quantum circuits, and nanotechnology.When building quantum computers, for example, the use of reversible logic is unavoidable.The structure of a reversible logic circuit is far more complex than that of an irreversible logic circuit.The multiplication operation is regarded as one of the most crucial in the ALU unit.In this paper, the Wallace tree method is utilized to minimize the depth of circuits in 8x 8 reversible unsigned multiplier circuits.The proposed design is an attempt to enhance design factors including the number of gates, garbage outputs, constant inputs, and quantum cost for an 8-bit Wallace Tree multiplier using reversible logic.The Proposed design offers 27% less quantum cost compared to the existing 8-bit Wallace tree multiplier design.
Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3/spl times/3 reversible gate termed TKS gate having two of its outputs working as 2:1 multiplexer. The proposed TKS gate is used to design a reversible half adder and is further used to design multiplexer based reversible full adder. The multiplexer based full adder is further used to design reversible 4/spl times/4 Array and modified Baugh Wooley multipliers. A novel 4/spl times/4 multiplier architecture with reversible logic is also proposed in which the partial products can be generated in parallel and their additions are reduced to logarithmic steps. In the proposed multiplier, all the operations are decomposed into levels, thereby significantly reducing the power consumption through a control circuitry which will switch off those levels which are not active. Thus, this work provides the initial threshold to building of complex systems which can execute more complicated operations. The reversible circuits designed and proposed in this paper form the basis for an ALU of a primitive quantum CPU.
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.
At present, Boolean algebra based computations by the use of silicon based semiconductor technology are irreversible in nature.This is due to the mismatch of number of inputs and outputs.Reversible logic circuit maps unique input to the output and ensure one to one mapping and basis for emerging applications like low-power design, quantum computation, optical computing, bioinformatics and nanotechnologies.In computing paradigm, Arithmetic Logic Unit (ALU) is one of the computing intensive building blocks of the computer that performs arithmetic and logical operations.This work understands and nurtures the necessity of reversible ALU for future revolutionary computing technologies.In this paper, a 4x4 reversible gate which alone performs arithmetic and logic operations is proposed and compared with other reversible gates like TSG, HNG and MKG, in terms of quantum cost, I/O lines and Taffoli gates.The results of different synthesis methods of 4x4 ALG using Revkit tool are studied.Proposed gate performs better than existing methods and ensures maximum logical operations like full adder, full subtractor and all logical operations with less hardware cost where other existing gates are not viable.
Reversible logic plays a crucial role in advancing future VLSI and quantum computing, where the optimization of design parameters like quantum cost, garbage outputs, and circuit complexity is essential. This paper introduces the design and implementation of an efficient 4×4 reversible multiplier on FPGA using Peres and TSG gates. The proposed architecture results in a 31.7 % reduction in quantum cost and enhances TRLIC by up to 30.6% compared to previous designs, while also decreasing garbage outputs and constant inputs. The design has been modeled, simulated, and validated on FPGA to verify its practical viability. Findings indicate that the proposed multiplier strikes a good balance among important parameters, surpassing traditional reversible multipliers in terms of efficiency and scalability. This positions it as a promising option for incorporation into low-power VLSI circuits and quantum arithmetic systems.
Reversible logic has emerged as a promising paradigm in various domains, such as low power VLSI design, quantum cellular automata, and nanotechnology-based systems. The arithmetic logic unit (ALU) is one of the main components of any central processing unit. In this paper we propose two new reversible ALUs using elementary quantum gates, with more functions compared to the existing designs. The results show that the proposed designs are better than the existing counterparts in terms of cost-metrics and the number of functions generated. The proposed reversible ALUs can be used in the implementation of quantum computers. All the designs are with nanometric scales.