Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

LDPC error correction for Gbit/s QKD

Alan Mink, Anastase Nakassis

Published May 22, 2014• 3 citations
Publisher

Abstract

Low Density Parity Check (LDPC) error correction is a one-way algorithm that has become popular for quantum key distribution (QKD) post-processing. Graphic processing units (GPUs) provide an interesting attached platform that may deliver high rates of error correction performance for QKD. We present the details of our various LDPC GPU implementations and both error correction and execution throughput performance that each achieves. We also discuss the potential for implementation on a GPU platform to achieve Gbit/s throughput.

DOI
10.1117/12.2050763

Related papers

Design of GPU-based platform for LDPC decoder

Cheng‐Chun Chang, Min-Yu Huang, Yang-Lang Chang

The needs for reliable and flexible downlink communications incorporated with high volume of satellite images in the ground station have inspired the demands for high performance and flexibility computing in the field of Earth remote sensing. Low-density parity-check (LDPC) codes have had a strong impact on achieving reliable communication links. Finding a fast and reconfigurable developing platform for designing high throughput LDPC decoders has become important. In this paper, a graphic processing unit (GPU) platform is proposed to realize this practical implementation. Experimental results show that the proposed GPU-based platform is compatible to serve as a high-throughput LDPC decoder.

IEEE International Geoscience and Remote Sensing Symposium (IGARSS)•Jul 1, 2011•4 citations

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Oscar Ferraz, Srinivasan Subramaniyan, Chinthala Ramesh +7 more

Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.

IEEE Communications Surveys & Tutorials•Nov 8, 2021•74 citations

High speed error correction for continuous-variable quantum key distribution with multi-edge type LDPC code

Xiangyu Wang, Yichen Zhang, Song Yu +1 more

Abstract Error correction is a significant step in postprocessing of continuous-variable quantum key distribution system, which is used to make two distant legitimate parties share identical corrected keys. We propose an experiment demonstration of high speed error correction with multi-edge type low-density parity check (MET-LDPC) codes based on graphic processing unit (GPU). GPU supports to calculate the messages of MET-LDPC codes simultaneously and decode multiple codewords in parallel. We optimize the memory structure of parity check matrix and the belief propagation decoding algorithm to reduce computational complexity. Our results show that GPU-based decoding algorithm greatly improves the error correction speed. For the three typical code rate, i.e., 0.1, 0.05 and 0.02, when the block length is 10 6 and the iteration number are 100, 150 and 200, the average error correction speed can be respectively achieved to 30.39 Mbits/s (over three times faster than previous demonstrations), 21.23 Mbits/s and 16.41 Mbits/s with 64 codewords decoding in parallel, which supports high-speed real-time continuous-variable quantum key distribution system.

arXiv:1711.01783•Scientific Reports•Jul 6, 2018•69 citations

Linear-time encoding and decoding of low-density parity-check codes

Mikael Simberg

Low-density parity-check (LDPC) codes had a renaissance when they were rediscovered in the 1990’s. Since then LDPC codes have been an important part of the field of error-correcting codes, and have been shown to be able to approach the Shannon capacity, the limit at which we can reliably transmit information over noisy channels. Following this, many modern communications standards have adopted LDPC codes. Error-correction is equally important in protecting data from corruption on a hard-drive as it is in deep-space communications. It is most commonly used for example for reliable wireless transmission of data to mobile devices. For practical purposes, both encoding and decoding need to be of low complexity to achieve high throughput and low power consumption. This thesis provides a literature review of the current state-of-the-art in encoding and decoding of LDPC codes. Message- passing decoders are still capable of achieving the best error-correcting performance, while more recently considered bit-flipping decoders are providing a low-complexity alternative, albeit with some loss in error-correcting performance. An implementation of a low-complexity stochastic bit-flipping decoder is also presented. It is implemented for Graphics Processing Units (GPUs) in a parallel fashion, providing a peak throughput of 1.2 Gb/s, which is significantly higher than previous decoder implementations on GPUs. The error-correcting performance of a range of decoders has also been tested, showing that the stochastic bit-flipping decoder provides relatively good error-correcting performance with low complexity. Finally, a brief comparison of encoding complexities for two code ensembles is also presented.

•Jan 20, 2015•0 citations

LDPC for QKD Reconciliation

Alan Mink, Anastase Nakassis

We present the Low Density Parity Check (LDPC) forward error correction algorithm adapted for the Quantum Key Distribution (QKD) protocol in a form readily applied by developers. A sparse parity check matrix is required for the LDPC algorithm and we suggest using some that have been defined by the IEEE and ETSI standards organizations for use in various communication protocols. We evaluate the QKD performance of these various parity check matrices as a function of the quantum bit error rate. We also discuss the computational precision required for this LPDC algorithm. As QKD evolves towards deployment, complete algorithm descriptions and performance analysis, as we present, will be required.

arXiv:1205.4977•May 22, 2012•14 citations

Simple rate-adaptive LDPC coding for quantum key distribution

Li, Mo, Chun-Mei Zhang, Zhen−Qiang Yin +3 more

Although quantum key distribution (QKD) comes from the development of quantum theory, the implementation of a practical QKD system does involve a lot of classical process, such as key reconciliation and privacy amplification, which is called post-processing. Post-processing has been a crucial element to high speed QKD systems, even the bottleneck of it because of its relatively high time consumption. Low density parity check (LDPC) is now becoming a promising approach of overcoming the bottleneck due to its good performance in processing throughput. In this article we propose and simulate an easily implemented but efficiently rate-adaptive LDPC coding approach of reconciliation, different from the previously proposed puncturing- and shortening-based approach. We also give a measure for choosing the optimal LDPC parameter for our rate-adaptive approach according to error rates.

arXiv:1505.06423•May 24, 2015•2 citations
Low Density Parity Check (LDPC) error correction is a one-way algorithm that has become popular for quantum key distribution (QKD) post-processing. Graphic processing units (GPUs) provide an interesting attached platform that may deliver high rates of error correction performance for QKD. We present the details of our various LDPC GPU implementations and both error correction and execution throughput performance that each achieves. We also discuss the potential for implementation on a GPU platform to achieve Gbit/s throughput.
The needs for reliable and flexible downlink communications incorporated with high volume of satellite images in the ground station have inspired the demands for high performance and flexibility computing in the field of Earth remote sensing. Low-density parity-check (LDPC) codes have had a strong impact on achieving reliable communication links. Finding a fast and reconfigurable developing platform for designing high throughput LDPC decoders has become important. In this paper, a graphic processing unit (GPU) platform is proposed to realize this practical implementation. Experimental results show that the proposed GPU-based platform is compatible to serve as a high-throughput LDPC decoder.
Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.
Abstract Error correction is a significant step in postprocessing of continuous-variable quantum key distribution system, which is used to make two distant legitimate parties share identical corrected keys. We propose an experiment demonstration of high speed error correction with multi-edge type low-density parity check (MET-LDPC) codes based on graphic processing unit (GPU). GPU supports to calculate the messages of MET-LDPC codes simultaneously and decode multiple codewords in parallel. We optimize the memory structure of parity check matrix and the belief propagation decoding algorithm to reduce computational complexity. Our results show that GPU-based decoding algorithm greatly improves the error correction speed. For the three typical code rate, i.e., 0.1, 0.05 and 0.02, when the block length is 10 6 and the iteration number are 100, 150 and 200, the average error correction speed can be respectively achieved to 30.39 Mbits/s (over three times faster than previous demonstrations), 21.23 Mbits/s and 16.41 Mbits/s with 64 codewords decoding in parallel, which supports high-speed real-time continuous-variable quantum key distribution system.
Low-density parity-check (LDPC) codes had a renaissance when they were rediscovered in the 1990’s. Since then LDPC codes have been an important part of the field of error-correcting codes, and have been shown to be able to approach the Shannon capacity, the limit at which we can reliably transmit information over noisy channels. Following this, many modern communications standards have adopted LDPC codes. Error-correction is equally important in protecting data from corruption on a hard-drive as it is in deep-space communications. It is most commonly used for example for reliable wireless transmission of data to mobile devices. For practical purposes, both encoding and decoding need to be of low complexity to achieve high throughput and low power consumption. This thesis provides a literature review of the current state-of-the-art in encoding and decoding of LDPC codes. Message- passing decoders are still capable of achieving the best error-correcting performance, while more recently considered bit-flipping decoders are providing a low-complexity alternative, albeit with some loss in error-correcting performance. An implementation of a low-complexity stochastic bit-flipping decoder is also presented. It is implemented for Graphics Processing Units (GPUs) in a parallel fashion, providing a peak throughput of 1.2 Gb/s, which is significantly higher than previous decoder implementations on GPUs. The error-correcting performance of a range of decoders has also been tested, showing that the stochastic bit-flipping decoder provides relatively good error-correcting performance with low complexity. Finally, a brief comparison of encoding complexities for two code ensembles is also presented.
We present the Low Density Parity Check (LDPC) forward error correction algorithm adapted for the Quantum Key Distribution (QKD) protocol in a form readily applied by developers. A sparse parity check matrix is required for the LDPC algorithm and we suggest using some that have been defined by the IEEE and ETSI standards organizations for use in various communication protocols. We evaluate the QKD performance of these various parity check matrices as a function of the quantum bit error rate. We also discuss the computational precision required for this LPDC algorithm. As QKD evolves towards deployment, complete algorithm descriptions and performance analysis, as we present, will be required.
Although quantum key distribution (QKD) comes from the development of quantum theory, the implementation of a practical QKD system does involve a lot of classical process, such as key reconciliation and privacy amplification, which is called post-processing. Post-processing has been a crucial element to high speed QKD systems, even the bottleneck of it because of its relatively high time consumption. Low density parity check (LDPC) is now becoming a promising approach of overcoming the bottleneck due to its good performance in processing throughput. In this article we propose and simulate an easily implemented but efficiently rate-adaptive LDPC coding approach of reconciliation, different from the previously proposed puncturing- and shortening-based approach. We also give a measure for choosing the optimal LDPC parameter for our rate-adaptive approach according to error rates.