Stochastic processes on quantum logics

Anatolij Dvurečenskij, Sylvia Pulmannová

David Deutsch

Claims that the standard procedure for testing scientific theories is inapplicable to Everettian quantum theory, and hence that the theory is untestable, are due to misconceptions about probability and about the logic of experimental testing. Refuting those claims by correcting those misconceptions leads to an improved theory of scientific methodology (based on Popper׳s) and testing, which allows various simplifications, notably the elimination of everything probabilistic from the methodology (‘Bayesian’ credences) and from fundamental physics (stochastic processes). • Everettian quantum theory is testable. • Stochastic theories suffer from a flaw in the logic of their testability. • Popper׳s methodology is needed to understand the testability of quantum theory.

C. Barnett, R. F. Streater, Ivan F. Wilde

Cameron J. Wellard, Lloyd C. L. Hollenberg

We examine a stochastic noise process that has a decohering effect on the average evolution of qubits in the quantum register of the solid state quantum computer proposed by Kane. We consider the effects of this process on the single qubit operations necessary to perform quantum logical gates and derive an expression for the fidelity of these gates in this system. We then calculate an upper bound on the level of this stochastic noise tolerable in a workable quantum computer.

E. B. Davies

Takeshi Onomi, Takaharu Kondo, Kiyotaka Nakajima

We report a design and an experimental result of an SFQ up/down counter for neural computation using stochastic logic. Neural computation using stochastic logic must accumulate the pulses in order to generate the membrane potential of a neuron. A high-speed up/down counter is necessary to achieve high-speed operation. The proposed up/down counter has two operation phases which are the accumulation of signals and the access of accumulation result. Even if the number of bit increases, the operation speed of the accumulation does not decrease in this method. A 4-bit up/down counter is fabricated using niobium-trilayer standard process and successfully demonstrated. The numerical simulation shows that the up/down counter can operate up to 70 GHz with an enough bias margin in the accumulation phase.