This article describes the different methods to design regular low density parity-check (LDPC) codes with large girth. In graph terms, this corresponds to designing bipartite undirected regular graphs with large girth. Large girth speeds the convergence of iterative decoding and improves the performance at least in the high SNR range, by slowing down the onsetting of the error floor. We reviewed several existing constructions from exhaustive search to highly structured designs based on Euclidean and projective finite geometries and combinatorial designs. We describe GB and TS LDPC codes and compared the BER performance with large girth to the BER performance of random codes. These studies confirm that in the high SNR regime these codes with high girth exhibit better BER performance. The regularity of the codes provides additional advantages that we did not explore in this article like the simplicity of their hardware implementation and fast encoding.
This article describes the different methods to design regular low density parity-check (LDPC) codes with large girth. In graph terms, this corresponds to designing bipartite undirected regular graphs with large girth. Large girth speeds the convergence of iterative decoding and improves the performance at least in the high SNR range, by slowing down the onsetting of the error floor. We reviewed several existing constructions from exhaustive search to highly structured designs based on Euclidean and projective finite geometries and combinatorial designs. We describe GB and TS LDPC codes and compared the BER performance with large girth to the BER performance of random codes. These studies confirm that in the high SNR regime these codes with high girth exhibit better BER performance. The regularity of the codes provides additional advantages that we did not explore in this article like the simplicity of their hardware implementation and fast encoding.
This paper,based on algebra and graph,proposes a method for constructing structured low-density parity-check(LDPC) codes.In this method,the authors design a connected graph with three kinds of special path to ensure that the Tanner graph of the parity check matrix mapped from the connected graph is without short cycles.The construction method results in two classes of(3,k)-regular quasi-cyclic LDPC codes with girth 8 and 12 respectively.Furthermore,by extending this construction method,two classes of LDPC codes with column weight 2,whose girths are respectively 16 and 24,can be obtained.The simulation studies show that these codes can achieve better performance than randomly constructed regular LDPC codes over AWGN channels with iterative decoding.At the BER of 10-5,the new proposed(3,6)-regular(4356,2205) QC-LDPC code performs 1.48dB from the Shannon limit.Moreover,it outperforms the random regular LDPC code of comparable parameters by 0.1dB.For the new proposed structured LDPC codes with column weight 2,they can achieve about 2dB coding gains with respect to the random regular LDPC codes with similar block lengths and code rates.
Low density parity check (LDPC) codes have stimulated a lot of interest in recent years due to their capacity approaching performance and availability of fast decoding algorithms. The existing encoding scheme for LDPC code usually incurs too high complexity and should be changed to encoding scheme with low complexity. An elementary turbo structured Tanner graph construction and encoding scheme for a family of regular LDPC codes attaining desired high girth is studied in this paper. The construction provides flexibility in choice of parameters like column weight (j > =2), row weight k and arbitrary girth g. Turbo structured low density parity check ( TS-LDPC) codes are regular LDPC codes with their Tanner graph consists of two trees connected by an interleaver. Linear complexity is attained with few alterations and restrictions of in Tanner graph of turbo structured LDPC codes. Simulation results demonstrates that not only the bit error rate (BER) performance of TSLDPC codes at low signal to noise ratio (SNR) is comparable with error performance of corresponding random LDPC codes, with better error performance at high SNR but linear encoding considerably reduces simulation time.
Two algebraic methods for systematic construction of structured regular and irregular low-density parity-check (LDPC) codes with girth of at least six and good minimum distances are presented. These two methods are based on geometry decomposition and a masking technique. Numerical results show that the codes constructed by these methods perform close to the Shannon limit and as well as random-like LDPC codes. Furthermore, they have low error floors and their iterative decoding converges very fast. The masking technique greatly simplifies the random-like construction of irregular LDPC codes designed on the basis of the degree distributions of their code graphs
Low Density Parity Check (LDPC) codes are specified by the parity check matrix H. Smaller girths in the Tanner graphs of LDPC codes prevent the sum-product algorithm from converging, i.e., short cycles in H-matrix degrade the performance of LDPC decoder. In this paper, we present an algorithm for constructing LDPC codes without short cycles. The H-matrix must be sufficiently sparse to increase the girth of a code. In this work, we present a simple method to increase the sparsity of matrix and provide lemmas to avoid short cycles of lengths 4 and 6. We design sub-matrices for column-weight two and column-weight three codes. This design makes use of a simple shifting function given by the proposed scheme. These are then combined into a final H-matrix using Gray code representations. The proposed method provides structured, regular codes with flexibility in code rates and code lengths. The regularity of these codes gives the advantages like simplicity of hardware implementation and fast encoding. Key words LDPC codes, Tanner Graph, Girth, Gray codes
In this paper we construct three types of low-density parity-check codes with column weight j = 3 based on geometries in graphical models. Low-density parity-check codes with j > 2 are desired because their minimum distance improves linearly with the code block length n. The codes we present here have girth 8 and girth 10. All codes are regular and well-structured. These codes have flexible block lengths and code rates, and may be used in the area of communications and data storage. Our simulation results show that they have better bit-error-rate decoding performance and lower error floors in additive white Gaussian noise channels than randomly constructed low-density parity-check codes.
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.