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Superconductor Science and Technology

Current recycling technique using capacitive grounding

Chen Kong Teh, Youichi Enomoto, Yoichi Okabe

Published Nov 7, 2003• 2 citations
Publisher

Abstract

Current recycling is an essential technique for realizing large-scale integrated single-flux-quantum circuits, since it can reduce bias current supply from several amperes to hundreds of milliamperes. Recently, there have been two reports proposing current recycling techniques. However, the fluctuation of global bias current, due to the switching of Josephson junctions, was not considered in these reports. Moreover, junctions cannot be grounded at the same point due to the use of isolated ground planes. In this paper, we propose a modified version of the current recycling technique using capacitive grounding, which will solve all these issues. We present an optimized driver and receiver for this technique. We have verified its workability and evaluated its characteristics by using several simulated tests, including evaluating bias set-up time, evaluating the relation of ground capacitance and signal capacitance to global bias margin, verifying its workability in a more complicated circuit, and performing high-speed test at frequencies up to 80 Gbps.

DOI
10.1088/0953-2048/16/12/042

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Current recycling is an essential technique for realizing large-scale integrated single-flux-quantum circuits, since it can reduce bias current supply from several amperes to hundreds of milliamperes. Recently, there have been two reports proposing current recycling techniques. However, the fluctuation of global bias current, due to the switching of Josephson junctions, was not considered in these reports. Moreover, junctions cannot be grounded at the same point due to the use of isolated ground planes. In this paper, we propose a modified version of the current recycling technique using capacitive grounding, which will solve all these issues. We present an optimized driver and receiver for this technique. We have verified its workability and evaluated its characteristics by using several simulated tests, including evaluating bias set-up time, evaluating the relation of ground capacitance and signal capacitance to global bias margin, verifying its workability in a more complicated circuit, and performing high-speed test at frequencies up to 80 Gbps.
An increase in bias currents supplied to single-flux-quantum (SFQ) circuits is a rising problem in building large-scale integrated SFQ circuits, because the magnetic fields generated by bias currents and ground return currents affect the circuit operation. Current recycling technique, which can drastically reduce the total bias current of SFQ circuits, is expected to be a very effective solution for large-scale SFQ circuits. To realize the current recycling technique, signal transmission between SFQ logic circuits located on different ground planes is required. Two types of inductively coupled pulse transfer circuits were examined in this study. One is composed of a simple JTL driver and a DC-SQUID receiver whose junctions are slightly under-damped to enhance the magnetic sensitivity of the SQUID. The other circuit is composed of an SFQ driver based on a delay flip-flop (DFF) and a SQUID receiver. The advantage of the DFF-based circuit is that the coupling time between the driver and the receiver can be increased to ensure appropriate switching in the receiver junction. Two types of transfer circuits were implemented using the SRL 2.5 kA/cm2Nb process and their correct operation was experimentally confirmed. Circuit structures for effective coupling of the SFQ pulse transfer were also investigated. It was shown that a ground plane boundary should be separated from a ground plane hole underneath coupling inductors to obtain high coupling factors.
As single flux quantum (SFQ) circuit complexities scale, larger bias currents are required. The large current produces excessive heat and greatly complicates the design process. Current recycling offers a solution by reducing the required bias current through serially biased circuit blocks. Serial biasing is typically achieved in homogeneous SFQ systems where similar bias currents are required in similar circuits. Each of these homogeneous circuits is often placed on different ground planes and serially biased to reuse the bias currents. To address heterogeneous circuits with varying bias current requirements, a novel serial biasing technique is proposed. An interface between the ground planes with unequal bias current is presented that exhibits a current balancing capability. The interface supplies additional current before passing the current to the next ground plane. The ground planes are arranged in ascending order of bias current to manage the complexity of these heterogeneous circuits. Using a one bit SFQ full adder as an example, the proposed approach demonstrates several key benefits: a 49% reduction in the number of driver-receiver pairs, a 6.5% reduction in power dissipation, and a 35% reduction in bias current across a heterogeneous SFQ circuit placed on three isolated ground planes. The performance, bias current margins, and methods for current reduction are also discussed, showcasing the effectiveness of current recycling in improving the efficiency of complex heterogeneous SFQ systems.
The practical implementation of RSFQ technology in most digital electronics application areas requires much more complexity than the presently developed circuits. There are two important issues in building large-scale RSFQ circuits: 1) the recycling of the bias currents and 2) the transfer of SFQ pulses between circuits located far apart. RSFQ circuits are well known to operate with DC current bias. Even though the DC current biasing is more forgiving than the problematic AC biasing, it can still be a big concern when the circuit size becomes large. Dramatic reduction of the total bias current can be achieved by biasing several RSFQ circuits in series, where each circuit is positioned on a separate ground plane. In this work, we have used magnetically coupled Josephson transmission lines as inputs and outputs of an isolated shift register to show the feasibility of using the concept of serial biasing in current recycling. The circuit was simulated, fabricated with Nb technology, and tested at a temperature of 4.2 K. Test results show that SFQ pulses were transferred into the shift register built on a separate ground plane, clocked through it, and sent out back to the circuit on the original ground plane. We also studied on how to transfer SFQ pulses over an extended length, an important issue in building large RSFQ circuits. We have designed the circuits to test our microstrip line and multichip module approaches. We designed, optimized, fabricated and tested the circuits. Test results show that SFQ pulses can be successfully transmitted over an extensive distance in a chip and between chips.
Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.
High-frequency input signals from room-temperature microwave sources present a major bottleneck for scaling qubit numbers in universal quantum computers. To address this challenge, we previously developed a superconducting single-flux quantum (SFQ) qubit control circuit (SQCC) capable of generating precise SFQ pulse sequences using only DC bias. This approach eliminates traditional microwave signal chains and enables scalable, low-loss DC-based interconnects. However, as the number of SQCCs increases, the total required bias current grows linearly, leading to significant cable-induced thermal dissipation that limits scalability. In this work, we propose and implement an architecture using recycled bias current to scale up multiple SQCCs (RB-MSQCC). Theoretical analysis indicates that the recycling method can reduce thermal load by a factor of 100 to 1000 compared to conventional biasing. A key enabler of this architecture is a custom-designed driver-receiver pair (DRP) cell, which supports SFQ signal transmission across isolated ground planes using the SIMIT Nb03 process. Based on this, we demonstrate a 4-bit RB-MSQCC prototype. Experimental results confirm stable SFQ pulse generation across all four channels, with output frequencies ranging from 3.42 to 5.27 GHz, consistent with prior results (2.40-8.11 GHz). These findings validate the feasibility and robustness of the proposed scheme under current fabrication constraints. Our study offers both theoretical and experimental support for scalable, energy-efficient SFQ-based qubit control, representing a critical step toward large-scale superconducting quantum processors.
We propose a new inductive- and resistive- (LR) biased low-power single-flux quantum (SFQ) circuit that has a dynamic resetting mechanism of the bias current. Because the bias current returns to the initial state rapidly by switching of a Josephson junction in the bias circuit after circuit operation, the operating frequency of the LR-biased SFQ circuit can be improved. We simulated a Josephson transmission line (JTL) that employs the proposed biasing scheme and evaluated the bias current recovery time. Circuit simulation results show that the bias current recovery time of the proposed circuit is improved by 10-20% compared to that of the conventional LR-biased JTL. We have designed and measured a 10-stage JTL and an 8-bit concurrent-flow shift register (SR) with the proposed biasing scheme. We have experimentally demonstrated operation of the JTL with the bias margin of ±29.4% at the operating frequency of up to 70.4 GHz and operation of the 8-bit SR up to 12.3 GHz by the on-chip high-speed test.