In this paper we present a novel reversible implementation of a square-root circuit with an array structure. In scientific computations such as numerical analysis, computer graphics, complex number computations, square root is an important operation. In classical irreversible arena we find different realizations of square root circuit. Since reversible circuit is emerging as an alternative to classical circuit, here we introduce a novel reversible realization of this operation. As a basic module, we propose a reversible controlled adder/subtractor (RCAS) block based on 2's Complement computation. In our design we use an array of such RCAS blocks which perform addition or subtraction based on the result generated from digit-by-digit square root operation. To our best knowledge this is the first methodical approach for implementing reversible square root circuit. The new structure of the circuit and different parameters - number of gates, garbage bits and quantum cost for n-bit realization is presented here.
In this paper we present a novel reversible implementation of a square-root circuit with an array structure. In scientific computations such as numerical analysis, computer graphics, complex number computations, square root is an important operation. In classical irreversible arena we find different realizations of square root circuit. Since reversible circuit is emerging as an alternative to classical circuit, here we introduce a novel reversible realization of this operation. As a basic module, we propose a reversible controlled adder/subtractor (RCAS) block based on 2's Complement computation. In our design we use an array of such RCAS blocks which perform addition or subtraction based on the result generated from digit-by-digit square root operation. To our best knowledge this is the first methodical approach for implementing reversible square root circuit. The new structure of the circuit and different parameters - number of gates, garbage bits and quantum cost for n-bit realization is presented here.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
Abstract — Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. This paper provides the basic reversible logic gates, which in designing of more complex system having reversible circuits as a primitive component and which can execute more complicated operations using quantum computers. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. This paper presents the data relating to the primitive reversible gates which are available in literature and helps researches in designing higher complex computing circuits using reversible gates.
Abstract — Reversible logic is one of the most important issue at present time and it has different areas for its application. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs This paper represents an another approach to realize 4 bit 2’s complement adder subtractor by using reversible logic gates like Feynman Gate, DKG gate and one control line. A also a new reversible gate DKFG is proposed. Keywords—Reversible logic, Basic Reversible Gates, 2’s Complement, Reversible full adder, Reversible full sub-
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.
In this research work, the transistor level implementation and QCA implementation of TR reversible gate are performed and a comparison between both techniques on the ground of Area is executed. In the later section, a new-fangled design of the reversible adder and subtractor RSG gate is presented. This novel architecture can perform addition and subtraction operation simultaneously, which was never performed before using any of the existing reversible circuits. The proposed novel reversible gate, which uses 2X2 quantum gates and has a quantum cost of five, can be operated as Reversible Half Adder as well as Half Subtractor concurrently. The reversible gate proposed in this research will find numerous applicability in several DSP applications where half adder and half subtractor operates simultaneously.