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IEEE Wireless Communications Letters

Turbo Adaptive Threshold Bit Flipping For LDPC Decoding

Mohamed Ismail, Justin P. Coon, Imran Ahmed, Simon M. D. Armour, Joseph P. McGeehan

Published Dec 8, 2012• 6 citations
Publisher

Abstract

In this paper, we present a novel bit flipping algorithm for high-throughput decoding of LDPC codes. The algorithm exploits the turbo principle to reduce the average number of iterations and employs a bit-local thresholding operation to remove the need for a block-wise minimum operation — which is common to many conventional bit flipping decoders — that hinders decoder throughput. Through simulations the proposed decoder is shown to achieve comparable bit-error rate performance to state-of-the-art techniques while requiring approximately half the number of iterations on average thus facilitating high-throughput decoding.

DOI
10.1109/wcl.2012.120312.120560

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In this paper, we present a novel bit flipping algorithm for high-throughput decoding of LDPC codes. The algorithm exploits the turbo principle to reduce the average number of iterations and employs a bit-local thresholding operation to remove the need for a block-wise minimum operation — which is common to many conventional bit flipping decoders — that hinders decoder throughput. Through simulations the proposed decoder is shown to achieve comparable bit-error rate performance to state-of-the-art techniques while requiring approximately half the number of iterations on average thus facilitating high-throughput decoding.
This letter presents two novel adaptive bit-local threshold bit-flipping algorithms for improving the hard-decision decoding performance of LDPC codes. The threshold of each bit can be changed adaptively to maximize the number of corrected errors during the iterations. The proposed methods require only logical operations during decoding and can be realized easily by hardware. Compared with the existing adaptive threshold BF algorithm, the proposed algorithms achieve better performance while removing the need for the delay-inducing global maximum operations, thus facilitating high-throughput decoding.
A novel bit-flipping (BF) algorithm with low complexity for high-throughput decoding of low-density parity-check (LDPC) codes is presented. At each iteration, a novel threshold pattern is used to determine the code bits whether to be flipped or not, and the flipping error probability is effectively decreased. Compared with the weighted BF algorithm and its modifications, the modified BF algorithm has significantly lower complexity and decoding time. Through simulations the proposed BF algorithm is shown to achieve excellent performance and fast convergence speed while maintaining significantly low complexity thus facilitating high-throughput decoding.
The bit-flipping (BF) algorithm for decoding of low-density parity-check (LDPC) codes requires less complex hardware than other decoding algorithms, but its error correcting performance needs to be improved. In this letter, a threshold adaptation scheme is applied to BF algorithm based decoding of LDPC codes. Our experiments show that the optimal threshold value for BF depends on the error conditions, and threshold adjustment during decoding helps to prevent meaningless no-flipping iterations. Based on these statistical observations, the adaptive threshold technique is proposed to pursue both the maximum error correcting capability and the fastest decoding convergence.
Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.
At present, various communication and storage systems have put forward high requirements on both the complexity and performance of low-density parity-check (LDPC) decoders. Bit flipping decoders are a good candidate for these applications. This letter proposes to utilize the column layered scheduling to speed up the convergence and improve the error correcting performance of existing bit flipping algorithms. As the information storage bit flipping (ISBF) algorithm generally performs the best, we investigate the layered ISBF (LISBF) algorithm in detail, including developing two efficient techniques for optimizing the computation of flipping thresholds: forward-backward computation and two-max computation. Simulation results on a (3, 6) LDPC code show that, compared to the ISBF algorithm, the LISBF algorithm can reduce the frame error rate by up to an order and reduce the average number of iterations by around 40%.
This paper proposes a modified weighted violation-based bit-flipping decoding algorithm for LDPC codes, and no soft information is required for decoding, Futhermore, in order to reduce the average number of iterations and decoding complexity, the threshold of judgement is set. Simulation results show that this modified algorithm could achieve much less number of iterations and better performance as compared with several soft-decision bit-flipping decoding algorithms for LDPC codes with large girth and low code rate.