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IEEE International Symposium on Circuits and Systems proceedings

High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders

Yaoyu Tao, Youn Sung Park, Zhengya Zhang

Published May 1, 2012• 16 citations
Publisher

Abstract

Nonbinary LDPC codes have shown superior performance, but decoding nonbinary codes is complex, incurring a long latency and a much degraded throughput. We propose a low-latency variable processing node by a skimming algorithm, together with a low-latency extended min-sum check processing node by prefetching and relaxing redundancy control. The processing nodes are jointly designed for an optimal pipeline schedule. This low-latency, high-throughput architecture is applied to a class of high-performance (2, dc)-regular nonbinary LDPC codes constructed based on their binary images. A conflict-free memory is proposed to resolve data hazards caused by the non-structured nature of these codes. A complete (2, 4)-regular, (960, 480) GF(64) nonbinary LDPC decoder is demonstrated on a Xilinx Virtex-5 FPGA. The decoder delivers an excellent error-correcting performance at a 9.76 Mb/s coded throughput, representing a significant improvement of state-of-the-art extended min-sum decoder implementations.

DOI
10.1109/iscas.2012.6271844

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Nonbinary LDPC codes have shown superior performance, but decoding nonbinary codes is complex, incurring a long latency and a much degraded throughput. We propose a low-latency variable processing node by a skimming algorithm, together with a low-latency extended min-sum check processing node by prefetching and relaxing redundancy control. The processing nodes are jointly designed for an optimal pipeline schedule. This low-latency, high-throughput architecture is applied to a class of high-performance (2, dc)-regular nonbinary LDPC codes constructed based on their binary images. A conflict-free memory is proposed to resolve data hazards caused by the non-structured nature of these codes. A complete (2, 4)-regular, (960, 480) GF(64) nonbinary LDPC decoder is demonstrated on a Xilinx Virtex-5 FPGA. The decoder delivers an excellent error-correcting performance at a 9.76 Mb/s coded throughput, representing a significant improvement of state-of-the-art extended min-sum decoder implementations.
Nonbinary low-density parity-check (NB-LDPC) codes constructed over GF(q) (q >; 2) can achieve higher coding gain than binary LDPC codes when the code length is moderate. A complete partial-parallel decoder architecture based on the Min-max algorithm is proposed for quasi-cyclic NB-LDPC codes in this paper. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm5) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out.
This paper addresses decoder design for nonbinary quasicyclic LDPC(QC-LDPC) codes based on the extended min-sum(EMS) algorithm.It is necessary to perform quantities of recursive computation among the message vector,and only one single step operations is utilized to complete the check node update,which leads to larger decoder latency.In this paper,the novel non-binary LDPC decoder architecture is proposed to overcome this problem.Based on the rules of forward-backward algorithm,we utilize three single step operations to complete the check node update and optimize the check node update step operation.The hardware resource consumption for check node update increases slightly,but the cycle required is reduced to 1/3 of general decoder structure.The variable node update unit with fully parallel computation is presented without forward-backward,which removes recursive computation among the message vector and is of low complexity and latency.Moreover,an FPGA implementation for a(480,360) nonbinary QC-LDPC code decoder over GF(16) is designed to demonstrate the efficiency of the presented techniques.Simulation results show that the proposed design scheme can triple throughput of the decoder at the cost of less hardware resource consumption.
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance.Although various kinds of low-complexity iterative decoding algorithms have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high complexity and long latency.In this brief, highly efficient check node processing scheme, which the processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are proposed.Compare with previous works, less than 52% could be reduced for the latency of check node unit.In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NB-QC-LDPC decoder.
Nonbinary low-density parity-check (LDPC) codes are of great interest due to their better performance cover binary ones when the code length is moderate. However, the cost of decoder implementation for these LDPC codes is still very high. In this paper, a low-complexity VLSI architecture for nonbinary LDPC decoders is presented. By exploiting the intrinsic shifting and symmetry properties of nonbinary quasi-cyclic LDPC (QC-LDPC) codes, significant reduction of memory size and routing complexity can be achieved. These unique features lead to two network-efficient decoder architectures for Class-I and Class-II nonbinary QC-LDPC codes, respectively. Comparison results with the state-of-the-art designs show that for the code example of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save up to 70.6% hardware required by switch network, which demonstrates the efficiency of the proposed technique. The proposed design for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% switch network complexity reduction compared with conventional approaches. Furthermore, with the help of a generator for possible solution sequences, both forward and backward steps can be eliminated to offer processing convenience of check node unit (CNU) blocks. Results show the proposed 32-ary (992, 496) rate-0.5 Class-II decoder can achieve 4.47 Mb/s decoding throughput at a clock speed of 150 MHz.
Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.
Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed -regular LDPC code partly parallel decoder architecture based on which we implement a -bit, rate- -regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of Mbps and achieves BER at 2 dB over AWGN channel while performing maximum decoding iterations.