Single flux quantum logic and its non-latching operation

Hiroki Kodaka, Yoichi Okabe

Naoki Takeuchi, A. Akahori, N. Mori +4 more

We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.

Pascal Febvre

Futoshi Furuta, A. Akahori, N. Mori +6 more

We report experimental demonstrations of logic functions based on single flux quantum logic with resettable latch (SFQ-RL) logic. SFQ-RL has been proposed as new SFQ logic, which enables us to initialize the whole circuit. This initialization function is essential for the state machine into which conventional SFQ logic is classified, and makes SFQ logic more applicable to a large-scale logic system, such as a processor. In addition, the function can prevent circuits from performing the failed operation caused by a trapped flux in storage loops. The logic consists of three primitives, which can compose any logic function. We have experimentally demonstrated the operation of "half adder" based on SFQ-RL with the bias margin of /spl plusmn/16%. In order to examine the function of initialization, we designed and evaluated a pseudo random sequence generator by numerical simulation. In addition, we experimentally confirmed the initialization of the generator and "circular buffer" with the bias margin of /spl plusmn/20%.

K. K. Likharev

Futoshi Furuta, Y. Suzuki, E Oya +5 more

We propose new logic circuits based on Single Flux Quantum logic with Resettable Latch (SFQ-RL). This new logic enables us to initialize the whole circuit and realize an inverter easily. This initialization function is needed for general state machines, in addition, suppressing the failed operation caused by a trapped flux in storage loops. SFQ-RL logic consists of three primitives of gates, "Latch (L)-gate", "Copy(C)-gate" and "OR (O)-gate". L-gate is a kind of flip-flop gate. The difference from a conventional RSFQ latch, "RS-FF" is that L-gate can be reset without emitting an output pulse using "Initialize" pulse. Our numerical simulation shows that the bias margin of L-gate is /spl plusmn/8%. C-gate and O-gate correspond to "Splitter" and "Confluence Buffer" in RSFQ logic, respectively. Every logic function can be realized by only the three primitives. We confirmed the operations, "AND" and "OR" with reasonable margins and speeds by the numerical calculation. We have experimentally demonstrated the logic function such as OR based on SFQ-RL logic. We confirmed the normal operation of the gate with the bias margin of /spl plusmn/25.9%.