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IEEE Transactions on Applied Superconductivity

Analysis of the threshold characteristics of the uniform Josephson flux shuttle

H.L. Ko

Published Jan 1, 1991• 3 citations
Publisher

Abstract

A general method for calculating the mode boundaries of a uniform flux shuttle and numerical techniques for computing these thresholds are presented. A number of examples of practical interest are given, including the current distribution in a shuttle due to a single vortex, and static margins of directly injected two-phase shift registers and magnetically clocked three-phase shift registers. Comparison with dynamic circuit simulations shows that the static thresholds are good approximations over a wide range of junction parameters.>

DOI
10.1109/77.107402

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IEEE Transactions on Electron Devices•Oct 1, 1980•15 citations
A general method for calculating the mode boundaries of a uniform flux shuttle and numerical techniques for computing these thresholds are presented. A number of examples of practical interest are given, including the current distribution in a shuttle due to a single vortex, and static margins of directly injected two-phase shift registers and magnetically clocked three-phase shift registers. Comparison with dynamic circuit simulations shows that the static thresholds are good approximations over a wide range of junction parameters.>
A shift register is described which employs as information bits the flux quantum vortices occurring in Josephson junctions of extended dimensions. The positions of the vortices can be controlled and manipulated by an appropriately designed circuit geometry and by application of currents and magnetic fields. The time required for switching of the position of a vortex can approach the period of the Josephson plasma oscillation (∼10 ps) and the intrinsic energy dissipation is typically ≲ 10-18J/shift.
This dissertation presents the design, fabrication, and testing of a flux-shuttle shift register and a discussion of computer architecture and systems for various superconducting digital logic families. While superconductive digital logic provides very fast switching speed (a few picoseconds), it is necessary to carefully consider the application and the computer architecture being used to implement a digital system when designing for maximum performance. The first part of this dissertation addresses architecture issues. First, a brief description of superconducting digital logic fundamentals is provided. The basic concepts of various techniques used in current high-performance computing systems are then presented. Since system architecture is greatly influenced by the characteristics of the logic family used, we then describe three superconducting logic types in detail. The characteristics of each of these logic families are examined, and their influence on architecture is discussed. The system requirements of general-purpose computing and digital signal processing are investigated. Due to the demands placed on random access memory by general-purpose computing, we conclude that the most practical digital system currently realizable in superconducting technology is based on digital signal processing (DSP). Finally, three example DSP systems are explored. Part II of this dissertation concentrates on the design, fabrication, and testing of a shift register, an important part of many DSP systems. Several shift registers using different logic types are evaluated. The design and testing of a flux-shuttle shift register using direct injection clocks are presented. The circuit was experimentally verified to work with wide operating margins at low speed. While simulations indicate that the shift register will operate at more than 60 GHz, high-speed test of the shift register was limited to 1 GHz by available test equipment.
Moats in superconducting ground planes are used to trap magnetic flux away from sensitive parts of superconductor integrated circuits. We simulate the effect of magnetic flux trapped in moats on the operating margins of ac-biased SFQ shift registers (ShReg) with two ground planes for various congruent moat geometries, moat sizes, locations in the ShReg cells, number and polarity of the trapped of fluxons. Using inductance extractor InductEx, we extract mutual couplings between the moats and the ShReg inductors and include them in the refined netlist. Then, we use JoSim to simulate the circuit operation and find the threshold ac clock amplitude above which the register starts to operate correctly. The relative change in this threshold is used to characterize the influence of flux trapping on the circuit operation. Monte-Carlo simulations are used to investigate the effect of the circuit parameter variations on the statistics of the threshold, using the standard deviation of the Josephson junction critical current and of the circuit inductance extracted from the fabrication process control monitors. The obtained distributions are compared with the independently measured distributions of the threshold amplitude for the individual cells of ac-biased shift registers with 108,500 Josephson junctions. The results show that flux trapping in properly designed moats have a very small effect on the operation margins of the large-scale shift registers whereas the main contribution to the cell-to-cell variation of the threshold comes from the variation of the junctions' critical currents.
Static and dynamic properties of an interferometer with five equal Josephson junctions are investigated as a single-flux quanta shift-register model. A flux quantum is stored in any loop without a bias current or magnetic field. A flux quantum is shifted from one interferometer loop to the adjacent one by applying a magnetic-field control pulse only to one in terferometer loop at a time. Shift current margins determined statically and dynamically are larger than about ±30 percent; the write current margins are ±25 percent. Within these tolerances, and for a maximum Josephson current density of 10 kA/ cm2, delays of 16 ps/bit, including shift and write, have been simulated.