Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IET Communications

Hybrid decoding of finite geometry low-density parity-check codes

Guanchang Li, Dong Li, Yang Wang, W B Sun

Published Jun 24, 2010• 5 citations
Publisher

Abstract

For finite geometry low-density parity-check codes, heavy row and column weights in their parity check matrix make the decoding with even min–Sum (MS) variants computationally expensive. To alleviate it, the authors present a class of hybrid schemes by concatenating a parallel bit flipping (BF) variant with an MS variant. Meanwhile, the BF variant, with much less computational complexity, attempts decoding the receive sequence firstly, and only decoding failure of the BF variant triggers the MS variant. Hence the BF variant performance heavily impacts the overall hybrid scheme, which is illustrated in two case studies. Computational and hardware complexity is then elaborated to justify the feasibility of the hybrid schemes. In most SNR region of interest, without compromising performance or convergence rate, the proposed hybrid schemes can save substantial computational complexity when compared with the MS variant decoding alone.

DOI
10.1049/iet-com.2009.0415

Related papers

Hybrid Decoding of Finite Geometry LDPC Codes

Guangwen Li, Dashe Li, Wang, Yuling +1 more

For finite geometry low-density parity-check codes, heavy row and column weights in their parity check matrix make the decoding with even Min-Sum (MS) variants computationally expensive. To alleviate it, we present a class of hybrid schemes by concatenating a parallel bit flipping (BF) variant with an Min-Sum (MS) variant. In most SNR region of interest, without compromising performance or convergence rate, simulation results show that the proposed hybrid schemes can save substantial computational complexity with respect to MS variant decoding alone. Specifically, the BF variant, with much less computational complexity, bears most decoding load before resorting to MS variant. Computational and hardware complexity is also elaborated to justify the feasibility of the hybrid schemes.

arXiv:0801.1208•Jan 8, 2008•0 citations

Improved parallel weighted bit flipping decoding of finite geometry LDPC codes

Guangwen Li, Dashe Li, Yuling Wang +1 more

To seek a decoding scheme with good performance, low complexity and fast convergence, we present an improved parallel weighted bit flipping (IPWBF) algorithm for finite geometry low-density parity-check codes whose parity check matrix is of heavy row and column weights. In the IPWBF, a bit flipping (BF) function and two parallel BF criteria, all of which scatter in the literature, are exploited jointly to serve our purpose. Meanwhile, differential evolution is used to optimize the involved parameters. Simulation results show that the proposed algorithm achieves an observable performance gain over its counterparts without any complexity penalty. Furthermore, with respect to other known low complexity decodings such as normalized BP-based, the IPWBF yields a new performance versus complexity tradeoff, that is, higher throughput at the expense of moderate performance loss.

International Conference on Communications and Networking in China (ChinaCom)•Aug 1, 2009•5 citations

An Efficient Decoding Algorithm for Finite-Geometry Low-Density Parity-Check Codes

Quan Zi-yi

Based on decoding performance,complexity and latency of finite-geometry low-density parity-check(FG-LDPC) codes,an efficient decoding algorithm is proposed.The new algorithm is a hybrid bit-flipping(BF)/majority-logic(MLG) decoding scheme.In BF decoding,an efficient method was explored to measure the reliability of the checks.At the completion of a small number of iterations,the output from BF decoding is decoded by MLG decoding.In the hybrid algorithm,there are no float operations.Simulation results show that the hybrid algorithm can provide 0.3?dB coding gain over weight bit-flipping(WBF) decoding.

Beijing Youdian Xueyuan xuebao•Jan 1, 2007•0 citations

A Improved Decoding Algorithm for Low-Density Parity-Check Codes

Wei Zhou, Aidong Men, Liye Zhao +1 more

Based on decoding performance, complexity and latency of finite-geometry low-density parity-check (LDPC) codes, an efficient decoding algorithm is proposed. The algorithm is a hybrid bit-flipping (BF)/majority-logic (MLG) algorithm. In the algorithm, there are two stages. At the first stage, a code is decoded with bit-flipping (BF) with a small fixed number of iterations. Then the output from bit-flipping (BF) decoder is decoded by majority-logic (MLG) decoding. And in bit-flipping (BF) decoding, a new method is used to find the least reliable position. In the hybrid algorithm, there aren't real operations. Simulation results show that the algorithm provides 0.3dB coding gain over weight bit-flipping (WBF) decoding, and within 1 dB away from sum-product algorithm (SPA) decoding.

IEEE International Conference on Communication Technology (ICCT)•Nov 1, 2006•0 citations

VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes

Junho Cho, Jonghong Kim, Wonyong Sung

VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.

IEEE Transactions on Circuits and Systems I Regular Papers•May 1, 2010•12 citations

Improved parallel weighted bit-flipping decoding algorithm for LDPC codes

Guanchang Li, G. Feng

Aiming at seeking a low-complexity decoder with fast decoding convergence speed for short or medium low-density parity-check (LDPC) codes, an improved parallel weighted bit-flipping (IPWBF) algorithm, which is applied flexibly for two classes of codes is presented here. For LDPC codes with low column weight in their parity check matrix, both bootstrapping and loop detection procedures, described in the existing literature, are included in IPWBF. Furthermore, a novel delay-handling procedure is introduced to prevent the codeword bits of high reliability from being flipped too hastily. For large column weight finite geometry LDPC codes, only the delay-handling procedure is included in IPWBF to show its effectiveness. Extensive simulation results demonstrate that the proposed algorithm achieves a good tradeoff between performance and complexity.

IET Communications•Jan 7, 2009•13 citations
For finite geometry low-density parity-check codes, heavy row and column weights in their parity check matrix make the decoding with even min–Sum (MS) variants computationally expensive. To alleviate it, the authors present a class of hybrid schemes by concatenating a parallel bit flipping (BF) variant with an MS variant. Meanwhile, the BF variant, with much less computational complexity, attempts decoding the receive sequence firstly, and only decoding failure of the BF variant triggers the MS variant. Hence the BF variant performance heavily impacts the overall hybrid scheme, which is illustrated in two case studies. Computational and hardware complexity is then elaborated to justify the feasibility of the hybrid schemes. In most SNR region of interest, without compromising performance or convergence rate, the proposed hybrid schemes can save substantial computational complexity when compared with the MS variant decoding alone.
For finite geometry low-density parity-check codes, heavy row and column weights in their parity check matrix make the decoding with even Min-Sum (MS) variants computationally expensive. To alleviate it, we present a class of hybrid schemes by concatenating a parallel bit flipping (BF) variant with an Min-Sum (MS) variant. In most SNR region of interest, without compromising performance or convergence rate, simulation results show that the proposed hybrid schemes can save substantial computational complexity with respect to MS variant decoding alone. Specifically, the BF variant, with much less computational complexity, bears most decoding load before resorting to MS variant. Computational and hardware complexity is also elaborated to justify the feasibility of the hybrid schemes.
To seek a decoding scheme with good performance, low complexity and fast convergence, we present an improved parallel weighted bit flipping (IPWBF) algorithm for finite geometry low-density parity-check codes whose parity check matrix is of heavy row and column weights. In the IPWBF, a bit flipping (BF) function and two parallel BF criteria, all of which scatter in the literature, are exploited jointly to serve our purpose. Meanwhile, differential evolution is used to optimize the involved parameters. Simulation results show that the proposed algorithm achieves an observable performance gain over its counterparts without any complexity penalty. Furthermore, with respect to other known low complexity decodings such as normalized BP-based, the IPWBF yields a new performance versus complexity tradeoff, that is, higher throughput at the expense of moderate performance loss.
Based on decoding performance,complexity and latency of finite-geometry low-density parity-check(FG-LDPC) codes,an efficient decoding algorithm is proposed.The new algorithm is a hybrid bit-flipping(BF)/majority-logic(MLG) decoding scheme.In BF decoding,an efficient method was explored to measure the reliability of the checks.At the completion of a small number of iterations,the output from BF decoding is decoded by MLG decoding.In the hybrid algorithm,there are no float operations.Simulation results show that the hybrid algorithm can provide 0.3?dB coding gain over weight bit-flipping(WBF) decoding.
Based on decoding performance, complexity and latency of finite-geometry low-density parity-check (LDPC) codes, an efficient decoding algorithm is proposed. The algorithm is a hybrid bit-flipping (BF)/majority-logic (MLG) algorithm. In the algorithm, there are two stages. At the first stage, a code is decoded with bit-flipping (BF) with a small fixed number of iterations. Then the output from bit-flipping (BF) decoder is decoded by majority-logic (MLG) decoding. And in bit-flipping (BF) decoding, a new method is used to find the least reliable position. In the hybrid algorithm, there aren't real operations. Simulation results show that the algorithm provides 0.3dB coding gain over weight bit-flipping (WBF) decoding, and within 1 dB away from sum-product algorithm (SPA) decoding.
VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.
Aiming at seeking a low-complexity decoder with fast decoding convergence speed for short or medium low-density parity-check (LDPC) codes, an improved parallel weighted bit-flipping (IPWBF) algorithm, which is applied flexibly for two classes of codes is presented here. For LDPC codes with low column weight in their parity check matrix, both bootstrapping and loop detection procedures, described in the existing literature, are included in IPWBF. Furthermore, a novel delay-handling procedure is introduced to prevent the codeword bits of high reliability from being flipped too hastily. For large column weight finite geometry LDPC codes, only the delay-handling procedure is included in IPWBF to show its effectiveness. Extensive simulation results demonstrate that the proposed algorithm achieves a good tradeoff between performance and complexity.