Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Applied Mechanics and Materials

A Soft-Input Soft-Output Decoding Algorithm for LDPC Codes Based on Euclidean Distance

Published Jun 1, 2011• 0 citations
Publisher

Abstract

Paper has been removed due to plagiarism. The original paper was in an extended form in: Published in IET Communications, Vol 5, Issue 16, pp 2364-2370, 2011 Received on 23rd November 2010 Revised on 21st April 2011 doi: 10.1049/iet-com.2010.1040 Euclidean distance soft-input soft-output decoding algorithm for low-density parity-check codes P.G. Farrell1, L.J. Arnone, J. Castineira Moreira

DOI
10.4028/www.scientific.net/amm.63-64.999

Related papers

Euclidean distance soft-input soft-output decoding algorithm for low-density parity-check codes

Patrick Guy Farrell, Leonardo J. Arnone, Jorge Castiñeira Moreira

A new antilog–sum algorithm for decoding error-correcting codes is described. The soft-input, soft-output (SISO) algorithm uses squared Euclidean distance as the metric, does not require knowledge of the signal-to-noise ratio of the received signal and is less complex to implement than other SISO algorithms. The results of simulations show that the performance is very close to that of the log–sum–product algorithm.

IET Communications•Nov 4, 2011•13 citations

A Soft-Input Soft-Output Decoding Algorithm for LDPC Codes

Lixin Wang

A new soft-input,soft-output algorithm for decoding LDPC codes is described in this paper.Using soft squared Euclidean distance as the metric,the algorithm realizes decoding by iterating the antilog-sum of the Euclidean distance.A simplified algorithm is also put forward to reduce computational complexity.The proposed algorithm does not require knowledge of the signal-to-noise ratio of the received signal and is less complex to implement than other soft decision algorithms.The results of simulation show that the performance is very close to that of sum-product algorithm while the computational complexity is sharply reduced.

Journal of Spacecraft TT&C Technology•Jan 1, 2011•0 citations

Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders

Leonardo J. Arnone, J. Castiñeira Moreira, Patrick Guy Farrell

Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.

IET Communications•Aug 14, 2012•5 citations

Computation of Parity Check Matrices for Binary EG-LDPC Codes used in Communication Systems

Jyothi Chinna Babu, C. Chinnapu Reddy

The Low Density Parity Check (LDPC) are direct codes, which are true block and Shannon Limit codes.These codes are attained least error floors of data bits for data transfer applications used in communication systems.However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time.This results the reduction of decoding time, low decoding latency, complexity and as well as least error floorings in communication, when the transmitted data contains multiple error bits.This paper is proposed to represent the majority logic decoding/detecting of LDPC codes.This paper proposes the Generation of Originator and Parity estimated matrices for the Binary LDPC Codes.Here, the proposed techniques are hard decision decrypting and soft decision decrypting schemes.These schemes uses majority logic decoding based on the data transmission and reception in communication channel.This paper also elaborates the effective calculation of Euclidean distance and algorithm for constructing the LDPC codes.

Helix•Feb 28, 2019•0 citations

Investigations on performance analysis of various soft decision based LDPC decoding algorithms

Michaelraj Kingston Roberts, Elizabeth Sunny

In a transmission system the data transmitted from a source to destination gets corrupted due to noise and other non-linearities of the channel. Error Control Coding is a promising technique to minimize such error probabilities. LDPC codes are widely used for many practical applications. They exhibit excellent decoding performance with reduced computational complexity. This paper focuses on research issues related to decoding of various Low-Density Parity-Check (LDPC) codes.

International Conference on Inventive Computing and Informatics (ICICI)•Nov 1, 2017•2 citations

Techniques for the decoding of low density parity check codes: efficient simulation, algorithm improvement and implementation

Babak Daneshrad, Enver Çavuş

After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area. This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.

•Jan 1, 2007•2 citations
Paper has been removed due to plagiarism. The original paper was in an extended form in: Published in IET Communications, Vol 5, Issue 16, pp 2364-2370, 2011 Received on 23rd November 2010 Revised on 21st April 2011 doi: 10.1049/iet-com.2010.1040 Euclidean distance soft-input soft-output decoding algorithm for low-density parity-check codes P.G. Farrell1, L.J. Arnone, J. Castineira Moreira
A new soft-input,soft-output algorithm for decoding LDPC codes is described in this paper.Using soft squared Euclidean distance as the metric,the algorithm realizes decoding by iterating the antilog-sum of the Euclidean distance.A simplified algorithm is also put forward to reduce computational complexity.The proposed algorithm does not require knowledge of the signal-to-noise ratio of the received signal and is less complex to implement than other soft decision algorithms.The results of simulation show that the performance is very close to that of sum-product algorithm while the computational complexity is sharply reduced.
Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.
The Low Density Parity Check (LDPC) are direct codes, which are true block and Shannon Limit codes.These codes are attained least error floors of data bits for data transfer applications used in communication systems.However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time.This results the reduction of decoding time, low decoding latency, complexity and as well as least error floorings in communication, when the transmitted data contains multiple error bits.This paper is proposed to represent the majority logic decoding/detecting of LDPC codes.This paper proposes the Generation of Originator and Parity estimated matrices for the Binary LDPC Codes.Here, the proposed techniques are hard decision decrypting and soft decision decrypting schemes.These schemes uses majority logic decoding based on the data transmission and reception in communication channel.This paper also elaborates the effective calculation of Euclidean distance and algorithm for constructing the LDPC codes.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area. This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.