This paper presents a new family of low-density parity-check (LDPC) code, the sparse parity-check matrix of which is constructed by self-defining non-diagonal identity sub-matrix that is a solution of the "n-queen problem". So this sub-matrix is called the Q-matrix and these LDPC codes are called the Q-matrixes LDPC codes. The Q-matrixes LDPC codes are good or very good codes with iterative decoding and their Tanner graphs are free of 4-lines cycle. Furthermore, they can be created in cycle form. Their encoding can be achieved in linear time. Especially, their code length and code rate can be flexible and quickly adjusted according to the practical situation, and the performance of high rate is also very good. The other unique excellence is that the large sparse parity-check matrixes of long Q-matrixes LDPC codes require very small storage space. The result of this paper is very significant not only for designing low complexity encoder, improving performance and reducing the complexity of the sum-product iterative decoding algorithm, but also for building practice system of encodable and decodable LDPC code.
This paper presents a new family of low-density parity-check (LDPC) code, the sparse parity-check matrix of which is constructed by self-defining non-diagonal identity sub-matrix that is a solution of the "n-queen problem". So this sub-matrix is called the Q-matrix and these LDPC codes are called the Q-matrixes LDPC codes. The Q-matrixes LDPC codes are good or very good codes with iterative decoding and their Tanner graphs are free of 4-lines cycle. Furthermore, they can be created in cycle form. Their encoding can be achieved in linear time. Especially, their code length and code rate can be flexible and quickly adjusted according to the practical situation, and the performance of high rate is also very good. The other unique excellence is that the large sparse parity-check matrixes of long Q-matrixes LDPC codes require very small storage space. The result of this paper is very significant not only for designing low complexity encoder, improving performance and reducing the complexity of the sum-product iterative decoding algorithm, but also for building practice system of encodable and decodable LDPC code.
This paper have developed farther the method of constructing sparse parity-check matrix (H-matrix) with determinate systemic structure as well as designing practice recursive encoding algorithm of the low-density parity-check (LDPC) codes. It discovers that the LDPC codes based on the circulant-shifted permutation Q-matrix created by N-queens searching algorithm perform better than them based on permutation identity matrix when Hd-matrix in H =[ HpHd] was constructed by using circulant-shifted permutation Q-matrix and identity matrix, respectively. It presents a simple and efficient algorithm of constructing Hdmatrix without 4-cycle and 6-cycle. The presented LDPC encoders require O(M) operation (M is check-bit size). They are rate-compatible and length- compatible encoders that can cover a very wide range of rate from 0.1 to 0.9 and length including any positive integer from 20 to infinity except prime number and multiple prime numbers. The presented LDPC codes with moderate length and 1/2 rate can achieve reliable performance - 10-5~10-6bit error rate (BER) - on an additive white Gaussian noise (AWGN) channel with signal-to-noise ratio (SNR) Eb/Noabout 1.42 dB1.
Low-density parity-check (LDPC) codes are a class of linear block codes with implementable decoders, which provide near-capacity performance on a large set of data-transmission and data-storage channels. LDPC codes were invented by Gallager in his 1960 doctoral dissertation and were mostly ignored during the 35 years that followed. One notable exception is the important work of Tanner in 1981, in which Tanner generalized LDPC codes and introduced a graphical representation of LDPC codes, now called a Tanner graph. The study of LDPC codes was resurrected in the mid 1990s with the work of MacKay, Luby, and others [3–6], who noticed, apparently independently of Gallager's work, the advantages of linear block codes with sparse (low-density) parity-check matrices. This chapter introduces LDPC codes and creates a foundation for further study of LDPC codes in later chapters. We start with the fundamental representations of LDPC codes via parity-check matrices and Tanner graphs. We then learn about the decoding advantages of linear codes that possess sparse parity-check matrices. We will see that this sparseness characteristic makes the code amenable to various iterative decoding algorithms, which in many instances provide near optimal performance. Gallager of course recognized the decoding advantages of such low-density parity-check codes and he proposed a decoding algorithm for the BI-AWGNC and a few others for the BSC. These algorithms have received much scrutiny in the past decade, and are still being studied.
The linear block code is called a binary Low-Density Parity-Check code if whose parity-check matrix is a sparse matrix. For the features of parity-check matrix, a LDPC code can be illustrated by a Tanner graph. Cycles, especially short cycles in the Tanner graph, lead to inefficient decoding and prevent the decoding algorithm from converging to the optimal decoding result. In this paper, a simple algorithm of constructing four-cycle-free regular A(n,d_v,d_c)LDPC codes, d_v3, is introduced. And we analyse the relationship between the performance and the cycle.
A novel and simple construction of regular LDPC codes was proposed, which used sparse binary sequences, through studying construction methods of LDPC codes. The distribution matrix of ones in parity-check matrix was introduced into the new construction. The cyclic cross correlation function and the cyclic auto correlation function were utilized to ensure that the girth of Tanner graph was eight. The new codes perform well using the sum-product algorithm for iterative decoding. Low encoding complexity can also be achieved due to the inherent quasi-cyclic structure of the LDPC codes.
Low-density parity check (LDPC) codes are a significant class of classical codes with many applications. Several good LDPC codes have been constructed using random, algebraic, and finite geometries approaches, with containing cycles of length at least six in their Tanner graphs. However, it is impossible to design a self-orthogonal parity check matrix of an LDPC code without introducing cycles of length four. In this paper, a new class of quantum LDPC codes based on lines and points of finite geometries is constructed. The parity check matrices of these codes are adapted to be self- orthogonal with containing only one cycle of length four in each pair of two rows. Also, the column and row weights, and bounds on the minimum distance of these codes are given. As a consequence, these codes can be encoded using shift-register encoding algorithms and can be decoded using iterative decoding algorithms over various quantum depolarizing channels.
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.